[Bug 227288] [New Port] cad/yosys: Framework for Verilog RTL synthesis

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=227288

Tobias Kortkamp <tobik at freebsd.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|New                         |Closed
         Resolution|---                         |Overcome By Events
           Assignee|ports-bugs at FreeBSD.org      |tobik at freebsd.org

--- Comment #1 from Tobias Kortkamp <tobik at freebsd.org> ---
There were two submissions of yosys.  I committed the other version in
ports r471844.  Sorry I didn't know this PR existed until now :-(

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