[Bug 230761] New port: cad/verilator

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=230761

            Bug ID: 230761
           Summary: New port: cad/verilator
           Product: Ports & Packages
           Version: Latest
          Hardware: Any
                OS: Any
            Status: New
          Severity: Affects Only Me
          Priority: ---
         Component: Individual Port(s)
          Assignee: ports-bugs at FreeBSD.org
          Reporter: kevinz5000 at gmail.com

Created attachment 196366
  --> https://bugs.freebsd.org/bugzilla/attachment.cgi?id=196366&action=edit
Git style diff

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

WWW: https://www.veripool.org/projects/verilator/wiki/Intro

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