[Bug 227288] [New Port] cad/yosys: Framework for Verilog RTL synthesis

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=227288

            Bug ID: 227288
           Summary: [New Port] cad/yosys: Framework for Verilog RTL
                    synthesis
           Product: Ports & Packages
           Version: Latest
          Hardware: Any
                OS: Any
            Status: New
          Severity: Affects Only Me
          Priority: ---
         Component: Individual Port(s)
          Assignee: freebsd-ports-bugs at FreeBSD.org
          Reporter: uddka at student.kit.edu

Created attachment 192236
  --> https://bugs.freebsd.org/bugzilla/attachment.cgi?id=192236&action=edit
shar archive of cad/yosys

Yosys is a framework for Verilog RTL synthesis. It currently has extensive
Verilog-2005 support and provides a basic set of synthesis algorithms for
various application domains.

- Process almost any synthesizable Verilog-2005 design
- Converting Verilog to BLIF / EDIF/ BTOR / SMT-LIB / simple RTL Verilog / etc.
- Built-in formal methods for checking properties and equivalence
- Mapping to ASIC standard cell libraries (in Liberty File Format)
- Mapping to Xilinx 7-Series and Lattice iCE40 FPGAs
- Foundation and/or front-end for custom flows

Yosys can be adapted to perform any synthesis job by combining the existing
passes (algorithms) using synthesis scripts and adding additional passes as
needed by extending the Yosys C++ code base.

WWW: http://www.clifford.at/yosys/

In the default configuration (when the option ABC is enabled) this port has a
runtime dependency on cad/abc (bug #227254).

portlint: looks fine.
poudriere: build successful.

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