[Bug 227282] [New Port] cad/arachne-pnr: Place and route tool for FPGAs
bugzilla-noreply at freebsd.org
bugzilla-noreply at freebsd.org
Wed Apr 4 11:38:40 UTC 2018
https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=227282
Bug ID: 227282
Summary: [New Port] cad/arachne-pnr: Place and route tool for
FPGAs
Product: Ports & Packages
Version: Latest
Hardware: Any
OS: Any
Status: New
Severity: Affects Only Me
Priority: ---
Component: Individual Port(s)
Assignee: freebsd-ports-bugs at FreeBSD.org
Reporter: uddka at student.kit.edu
Created attachment 192206
--> https://bugs.freebsd.org/bugzilla/attachment.cgi?id=192206&action=edit
shar archive of cad/arachne-pnr
Arachne-pnr implements the place and route step of the hardware compilation
process for FPGAs. It accepts as input a technology-mapped netlist in BLIF
format, as output by the Yosys synthesis suite for example. It currently
targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a
textual bitstream representation for assembly by the IceStorm icepack command.
The output of icepack is a binary bitstream which can be uploaded to a hardware
device.
Together, Yosys, arachne-pnr and IceStorm provide an fully open-source
Verilog-to-bistream tool chain for iCE40 1K and 8K FPGA development.
WWW: https://github.com/cseed/arachne-pnr
This port requires the chip-db files from devel/icestorm to build (bug
#226711).
portlint: looks fine.
poudriere: build successful.
--
You are receiving this mail because:
You are the assignee for the bug.
More information about the freebsd-ports-bugs
mailing list