ports/138129: [patch] Update misc/cpuid to support newer Intel processors
Andrew Brampton
brampton at gmail.com
Mon Aug 24 10:10:02 UTC 2009
>Number: 138129
>Category: ports
>Synopsis: [patch] Update misc/cpuid to support newer Intel processors
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: freebsd-ports-bugs
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: update
>Submitter-Id: current-users
>Arrival-Date: Mon Aug 24 10:10:01 UTC 2009
>Closed-Date:
>Last-Modified:
>Originator: Andrew Brampton
>Release: FreeBSD 7.2
>Organization:
>Environment:
>Description:
The tool misc/cpuid does not list the features on newer Intel CPUs.
>How-To-Repeat:
Run cpuid on a new Intel machine and it will report many of the features as unknown.
>Fix:
I have used the latest Intel spec sheet and added many of the missing features. I have also corrected some of the old ones which appeared to have been originally typed wrong.
Patch attached with submission follows:
--- cpuid.c.orig2 2009-08-24 00:14:21.000000000 +0100
+++ cpuid.c 2009-08-24 10:19:32.000000000 +0100
@@ -3,16 +3,17 @@
* Updated 24 Apr 2001 to latest Intel CPUID spec
* Updated 22 Dec 2001 to decode Intel flag 28, hyper threading
* Updated 1 Jan 2002 to cover AMD Duron, Athlon
+ * Updated 24 Aug 2009 to decode additional Intel flags
* May be used under the terms of the GNU Public License (GPL)
* Reference documents:
- * ftp://download.intel.com/design/pro/applnots/24161809.pdf (AP-485)
+ * http://www.intel.com/Assets/PDF/appnote/241618.pdf (AP-485 August 2009)
* http://developer.intel.com/design/Pentium4/manuals/24547103.pdf
* http://developer.intel.com/design/pentiumiii/applnots/24512501.pdf (AP-909)
* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/20734.pdf
* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf
- *
+ *
*/
#include <stdio.h>
@@ -144,24 +145,35 @@
};
char *Intel_feature_flags2[32] = {
- "SSE3 SSE3 extensions",
+ "SSE3 SSE3 extensions",
+ "PCLMULDQ PCLMULDQ instruction",
+ "DTES64 64-bit debug store",
+ "MONITOR MONITOR/MWAIT instructions",
+ "DS-CPL CPL Qualified Debug Store",
+ "VMX Virtual Machine Extensions",
+ "SMX Safer Mode Extension",
+ "EST Enhanced Intel SpeedStep Technology",
+ "TM2 Thermal Monitor 2",
+ "SSSE3 Supplemental Streaming SIMD Extension 3",
+ "CNXT-ID L1 Context ID",
NULL,
NULL,
- "MONITOR MONITOR/MWAIT instructions",
- "DS-CPL CPL Qualified Debug Store",
+ "CX16 CMPXCHG16B",
+ "xTPR Send Task Priority messages",
+ "PDCM Perfmon and debug capability",
NULL,
NULL,
- "EST Enhanced Intel SpeedStep Technology",
- "TM2 Thermal Monitor 2",
+ "DCA Direct Cache Access",
+ "SSE4.1 Streaming SIMD Extension 4.1",
+ "SSE4.1 Streaming SIMD Extension 4.2",
+ "x2APIC Extended xAPIC support",
+ "MOVBE MOVBE instruction",
+ "POPCNT POPCNT instruction",
NULL,
- "CID Context ID",
- NULL,
- NULL,
- "CX16 CMPXCHG16B",
- "xTPR Send Task Priority messages",
- NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+ "AES AES Instruction",
+ "XSAVE XSAVE/XSTOR states",
+ "OSXSAVE OS-enabled extended state managerment",
+ NULL, NULL, NULL, NULL
};
char *Intel_ext_feature_flags[32] = {
@@ -180,7 +192,7 @@
char *Intel_ext_feature_flags2[32] = {
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
"LAHF LAHF/SAHF available in IA-32e mode",
NULL, NULL, NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
@@ -520,18 +532,30 @@
case 0x4:
printf("Data TLB: 4MB pages, 4-way set assoc, 8 entries\n");
break;
+ case 0x5:
+ printf("Data TLB: 4MB pages, 4-way set assoc, 32 entries\n");
+ break;
case 0x6:
printf("1st-level instruction cache: 8KB, 4-way set assoc, 32 byte line size\n");
break;
case 0x8:
printf("1st-level instruction cache: 16KB, 4-way set assoc, 32 byte line size\n");
break;
+ case 0x9:
+ printf("1st-level instruction cache: 32KB, 4-way set assoc, 64 byte line size\n");
+ break;
case 0xa:
printf("1st-level data cache: 8KB, 2-way set assoc, 32 byte line size\n");
break;
case 0xc:
printf("1st-level data cache: 16KB, 4-way set assoc, 32 byte line size\n");
break;
+ case 0xd:
+ printf("1st-level data cache: 16KB, 4-way set assoc, 64 byte line size, ECC\n");
+ break;
+ case 0x21:
+ printf("256-KB L2 (MLC), 8-way set associative, 64 byte line size\n");
+ break;
case 0x22:
printf("3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64-byte line size\n");
break;
@@ -553,12 +577,21 @@
case 0x39:
printf("2nd-level cache: 128-KB, 4-way set associative, sectored cache, 64-byte line size\n");
break;
+ case 0x3a:
+ printf("2nd-level cache: 192-KB, 6-way set associative, sectored cache, 64-byte line size\n");
+ break;
case 0x3b:
printf("2nd-level cache: 128-KB, 2-way set associative, sectored cache, 64-byte line size\n");
break;
case 0x3c:
printf("2nd-level cache: 256-KB, 4-way set associative, sectored cache, 64-byte line size\n");
break;
+ case 0x3d:
+ printf("2nd-level cache: 384-KB, 6-way set associative, sectored cache, 64-byte line size\n");
+ break;
+ case 0x3e:
+ printf("2nd-level cache: 512-KB, 4-way set associative, sectored cache, 64-byte line size\n");
+ break;
case 0x40:
printf("No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache\n");
break;
@@ -583,23 +616,58 @@
case 0x47:
printf("3rd-level cache: 8MB, 8-way set associative, 64-byte line size\n");
break;
+ case 0x48:
+ printf("2nd-level cache: 3MB, 12-way set associative, 64-byte line size, unified on die\n");
+ break;
+ case 0x49:
+ /* TODO The code needs to be slightly restructured so we can check family and model here */
+ printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon MP, Family 0Fh, Model 06h\n");
+ printf("OR 2nd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
+ break;
+ case 0x4a:
+ printf("3rd-level cache: 6MB, 12-way set associative, 64-byte line size\n");
+ break;
+ case 0x4b:
+ printf("3rd-level cache: 8MB, 16-way set associative, 64-byte line size\n");
+ break;
+ case 0x4c:
+ printf("3rd-level cache: 12MB, 12-way set associative, 64-byte line size\n");
+ break;
+ case 0x4d:
+ printf("3rd-level cache: 16MB, 16-way set associative, 64-byte line size\n");
+ break;
+ case 0x4e:
+ printf("3rd-level cache: 6MB, 24-way set associative, 64-byte line size\n");
+ break;
case 0x50:
- printf("Instruction TLB: 4KB and 2MB or 4MB pages, 64 entries\n");
+ printf("Instruction TLB: 4KB, 2MB or 4MB pages, fully assoc., 64 entries\n");
break;
case 0x51:
- printf("Instruction TLB: 4KB and 2MB or 4MB pages, 128 entries\n");
+ printf("Instruction TLB: 4KB, 2MB or 4MB pages, fully assoc., 128 entries\n");
break;
case 0x52:
- printf("Instruction TLB: 4KB and 2MB or 4MB pages, 256 entries\n");
+ printf("Instruction TLB: 4KB, 2MB or 4MB pages, fully assoc., 256 entries\n");
+ break;
+ case 0x55:
+ printf("Instruction TLB: 2MB or 4MB pages, fully assoc., 7 entries\n");
+ break;
+ case 0x56:
+ printf("Data TLB: 4MB pages, 4-way set associative, 16 entries\n");
+ break;
+ case 0x57:
+ printf("Data TLB: 4KB pages, 4-way set associative, 16 entries\n");
+ break;
+ case 0x5a:
+ printf("Data TLB: 2MB or 4MB pages, 4-way set associative, 32 entries\n");
break;
case 0x5b:
- printf("Data TLB: 4KB and 4MB pages, fully assoc., 64 entries\n");
+ printf("Data TLB: 4KB or 4MB pages, fully assoc., 64 entries\n");
break;
case 0x5c:
- printf("Data TLB: 4KB and 4MB pages, fully assoc., 128 entries\n");
+ printf("Data TLB: 4KB or 4MB pages, fully assoc., 128 entries\n");
break;
case 0x5d:
- printf("Data TLB: 4KB and 4MB pages, fully assoc., 256 entries\n");
+ printf("Data TLB: 4KB or 4MB pages, fully assoc., 256 entries\n");
break;
case 0x60:
printf("1st-level data cache: 16-KB, 8-way set associative, sectored cache, 64-byte line size\n");
@@ -614,13 +682,16 @@
printf("1st-level data cache: 32KB, 4-way set assoc, 64 byte line size\n");
break;
case 0x70:
- printf("Trace cache: 12K-micro-op, 4-way set assoc\n");
+ printf("Trace cache: 12K-micro-op, 8-way set assoc\n");
break;
case 0x71:
- printf("Trace cache: 16K-micro-op, 4-way set assoc\n");
+ printf("Trace cache: 16K-micro-op, 8-way set assoc\n");
break;
case 0x72:
- printf("Trace cache: 32K-micro-op, 4-way set assoc\n");
+ printf("Trace cache: 32K-micro-op, 8-way set assoc\n");
+ break;
+ case 0x73:
+ printf("Trace cache: 64K-micro-op, 8-way set assoc\n");
break;
case 0x78:
printf("2nd-level cache: 1MB, 4-way set assoc, 64 byte line size\n");
@@ -629,19 +700,19 @@
printf("2nd-level cache: 128KB, 8-way set assoc, sectored, 64 byte line size\n");
break;
case 0x7a:
- printf("2nd-level cache: 256KB, 8-way set assoc, sectored, 64 byte line size\n");
+ printf("2nd-level cache: 256KB, 8-way set assoc, sectored, 64 byte line size\n");
break;
case 0x7b:
printf("2nd-level cache: 512KB, 8-way set assoc, sectored, 64 byte line size\n");
break;
case 0x7c:
- printf("2nd-level cache: 1MB, 8-way set assoc, sectored, 64 byte line size\n");
+ printf("2nd-level cache: 1MB, 8-way set assoc, sectored, 64 byte line size\n");
break;
case 0x7d:
- printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
+ printf("2nd-level cache: 2-MB, 8-way set associative, 64-byte line size\n");
break;
case 0x7f:
- printf("2nd-level cache: 512KB, 2-way set assoc, 64 byte line size\n");
+ printf("2nd-level cache: 512KB, 2-way set assoc, 64 byte line size\n");
break;
case 0x82:
printf("2nd-level cache: 256KB, 8-way set assoc, 32 byte line size\n");
@@ -664,9 +735,66 @@
case 0xB0:
printf("Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries\n");
break;
+ case 0xB1:
+ printf("Instruction TLB: 2MB Pages (8 entries) or 4MB pages (4 entries), 4-way set associative\n");
+ break;
+ case 0xB2:
+ printf("Instruction TLB: 4-KB Pages, 4-way set associative, 64 entries\n");
+ break;
case 0xB3:
printf("Data TLB: 4-KB Pages, 4-way set associative, 128 entries\n");
break;
+ case 0xB4:
+ printf("Data TLB: 4-KB Pages, 4-way set associative, 256 entries\n");
+ break;
+ case 0xCA:
+ printf("Shared 2nd-level TLB: 4-KB Pages, 4-way set associative, 512 entries\n");
+ break;
+ case 0xD0:
+ printf("3rd-level cache: 512KB, 4-way set associative, 64-byte line size\n");
+ break;
+ case 0xD1:
+ printf("3rd-level cache: 1MB, 4-way set associative, 64-byte line size\n");
+ break;
+ case 0xD2:
+ printf("3rd-level cache: 2MB, 4-way set associative, 64-byte line size\n");
+ break;
+ case 0xD6:
+ printf("3rd-level cache: 1MB, 8-way set associative, 64-byte line size\n");
+ break;
+ case 0xD7:
+ printf("3rd-level cache: 2MB, 8-way set associative, 64-byte line size\n");
+ break;
+ case 0xD8:
+ printf("3rd-level cache: 4MB, 8-way set associative, 64-byte line size\n");
+ break;
+ case 0xDC:
+ printf("3rd-level cache: 1.5MB, 12-way set associative, 64-byte line size\n");
+ break;
+ case 0xDD:
+ printf("3rd-level cache: 3MB, 12-way set associative, 64-byte line size\n");
+ break;
+ case 0xDE:
+ printf("3rd-level cache: 6MB, 12-way set associative, 64-byte line size\n");
+ break;
+ case 0xE2:
+ printf("3rd-level cache: 2MB, 16-way set associative, 64-byte line size\n");
+ break;
+ case 0xE3:
+ printf("3rd-level cache: 4MB, 16-way set associative, 64-byte line size\n");
+ break;
+ case 0xE4:
+ printf("3rd-level cache: 8MB, 16-way set associative, 64-byte line size\n");
+ break;
+ case 0xEA:
+ printf("3rd-level cache: 12MB, 24-way set associative, 64-byte line size\n");
+ break;
+ case 0xEB:
+ printf("3rd-level cache: 18MB, 24-way set associative, 64-byte line size\n");
+ break;
+ case 0xEC:
+ printf("3rd-level cache: 24MB, 24-way set associative, 64-byte line size\n");
+ break;
case 0xF0:
printf("64-byte prefetching\n");
break;
>Release-Note:
>Audit-Trail:
>Unformatted:
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