Synopsis: [NEW PORT] cad/gplcver: A Verilog HDL simulator Responsible-Changed-From-To: freebsd-ports-bugs->jylefort Responsible-Changed-By: jylefort Responsible-Changed-When: Sat May 14 14:08:57 GMT 2005 Responsible-Changed-Why: Take. http://www.freebsd.org/cgi/query-pr.cgi?pr=80968