Intel TurboBoost in practice

Alexander Motin mav at
Tue Jul 27 18:44:55 UTC 2010

Alan Cox wrote:
> On Mon, Jul 26, 2010 at 9:11 AM, Alexander Motin <mav at
> <mailto:mav at>> wrote:
>     In that case using C2 or C3 predictably caused small performance reduce,
>     as after falling to sleep, CPU needs time to wakeup. Even if tested CPU0
>     won't ever sleep during test, it's TLB shutdown IPIs to other cores
>     still probably could suffer from waiting other cores' wakeup.
> In the deeper sleep states, are the TLB contents actually maintained
> while the processor sleeps?  (I notice that in some configurations, we
> actually flush dirty data from the cache before sleeping.)

As I understand, we flush caches only as last resort, if platform does
not supports special techniques, such as disabling arbitration or making
CPU to wake up on bus mastering. But same ACPI C-states could map into
different CPU C-states. Some of these CPU states (like C6) could imply
caches invalidation, though I am not sure it can be seen outside.

ACPI 3.0 specification tells nothing about TLBs, so I am not sure we can
count on their invalidation, except we do it ourselves, like it is done
for caches when CPU can't keep their coherency while sleeping.

Alexander Motin

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