Bad performance on alpha? (make buildworld)
Petri Helenius
pete at he.iki.fi
Wed Feb 25 01:25:53 PST 2004
Peter Jeremy wrote:
>Recent iA32 implementations (basically anything more recent than a
>PII) are RISC cores which directly execute a subset of the iA32
>instruction set with the remainder handled by microcode. You get
>quite respectable results by treating it as a load/store RISC
>architecture and relying on the L1 cache to handle the register spills
>
>
This probably invites the question, what, if anything people like me who
are interested in getting the maximum performance out of any hardware
our things run on (maybe with the exception of the low-MHz embedded
stuff :-), is there any good tutorials/books on the subject what kind of
things to avoid when looking for optimal performance. The tightest loops
mostly do counter rolling, comparisons and pattern matching and we have
good mileage on getting performance gains by minimizing writing to
memory when there are other options like arithmetic on the fly.
One specific question that also comes to mind is if there is benefit on
the more modern, SSE enabled code, to excersise floating point in
balance with 64bit long long integers or does that gain performance only
if the code is compiled without SSE?
Pete
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