Bad performance on alpha? (make buildworld)

[Charles Swiger]

On Feb 24, 2004, at 3:26 PM, Nikos Ntarmos wrote:
> IIRC the 600MHz EV56's performance wrt integer operations (such as
> compiling) is somewhere in the vicinity of a 400MHz P-II, so the
> difference you see in turn-around times when buildworld'ing isn't
> quite that big. If the operations were identical, you should see
> better times when building on the alpha. However, also take into
> account that compiling (and optimizing) for a RISC CPU, apart from
> generating larger binaries, is AFAIK supposedly more difficult than
> compiling (and optimizing) for a CISC CPU.

I'm afraid you've got this backwards.  :-)

The primary attributes of RISC architectures, namely lots of registers, 
a relatively simple but orthagonal instruction set, and a relatively 
fast clock rate / CPI ~= 1.0 / a short pipeline make it far easier for 
the compiler to generate and optimize code.

CISC architectures make the compilers job much harder because they tend 
to require lots of register spills, they tend to have very long 
pipelines which involve hazards and require a lot of instruction 
reordering to avoid stalling the pipeline to often.  The amount of CPU 
clocks it takes per instruction (CPI) often varies on CISC as is 
generally much larger than ~1.0, and sometimes varies from CPU model to 
CPU model making it far more difficult to determine the "fastest" 
instruction sequence.

At a broader level, RISC closely matches the intermediate code model 
compilers work with than CISC does, which makes it easier to generate 
target code from the intermediate code.  Often, on RISC there is little 
difference between the two, just as there is less difference between 
optimized and unoptimized code, whereas on CISC there is a lot more 
work to be done in order to get optimized code working with comparible 
efficiency.

-- 
-Chuck