MUSL math functions

Bruce Evans brde at
Sun Nov 10 17:55:04 UTC 2013

On Sun, 10 Nov 2013, David Chisnall wrote:

> On 8 Nov 2013, at 08:50, David Schultz <das at FreeBSD.ORG> wrote:
>> However, several things have happened since then. For one, years
>> have passed and there's still quite a bit of work to do. For two,
>> the only ld128 platform, sparc64, doesn't look as important as it
>> used to be. For a long time, we had trouble even finding a viable
>> test machine. Therefore, I think any incremental improvement would
>> be welcome -- even if it means doing ld80 only.

> The PowerPC SysV ABI says that it's ld128 - we only use 64 bit because of lack of compiler support when the architecture was brought up, every other OS uses 128 bit (although I think PPC 128-bit floats are not quite the same as IEEE 128-bit floats, which may cause some problems).  It's quite likely that we'll change it to ld128 at some point, although that will involve some ABI breakage which is unfortunate.

One net reference says that it is the same as sparc, but wikipedia
says that it is double-double and gcc implements this.  An ibm reference
says that sparc has [only] 64-bit registers.  Double-double in software
would be horrible, possibly slower than IEEE in software on sparc64
where ld128 is about 100 times slower than double precision (old
sparc64 is several thousand times slower in nanoseconds than modern
i387 with long double precision for both).  Double-double is not
supported by FreeBSD libm.

Sparc64 defines IEEE format in hardware, but no old gcc and current
wikipedia say that no sparc CPU ever implemented it.  When not emulated
via libcalls, it is emulated via traps; this is slower but easier to

> ARMv8 is ld128 and, although it support hasn't landed yet (it's under development), it is likely to be a very important platform for FreeBSD in coming years.
> MIPS is also ld128 on most systems, but the fact that there is no 128-bit floating point hardware for MIPS (except in one ASE, where there is one 128-bit floating point accumulator register) makes this quite a silly choice, so it will probably stay ld64.

Does anyone have it in hardware?  Wikipedia doesn't mention either arm or
mips under where I found this for powerpc (Quadruple precision floating-
point format).  Searching for it for arm gives wikipedia at the top again.
It says that arm v8-A has 32x 128-bit SIMD registers and supports double
precision floating point.  Intel didn't bother with it for 256-bit AVX
registers.  gcc has some support for it in software on x86.

It was silly on old sparc too.  Unfortunately, some APIs encourage use
of long double, so when it is excessively wide these are slow.


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