Call for performance evaluation: net.isr.direct (fwd)

Bruce Evans bde at zeta.org.au
Fri Oct 14 02:42:02 PDT 2005


On Fri, 14 Oct 2005, Poul-Henning Kamp wrote:

> In message <17230.62415.991707.840932 at grasshopper.cs.duke.edu>, Andrew Gallatin
> writes:
>
>> Linux already takes care of syncing the TSC between SMP cpus, so we
>> know it is possible.  This seems like a much more doable optimization.
>> And it is likely to have other benefits..

The timestamps in mi_switch() are taken on the same CPU and only their
differences are used, so they don't even need to be synced.  It they
use the TSC, then the TSCs just need to have the same almost-constant
frequency (or different almost-constant frequencies if timecounters
werre per-CPU).

> Validating that the TSC is reliable is a nontrivial task which requires
> access to a lot of NDA information and an extensive positive/negative
> list of chips and chipsets.

It only requires comparsion with another time source over a sufficently
long enough time and large enough set of operating environments.  This
is hard to automate.  I compare with a local ntp server with a known
good TSC.

> Even in the most recent chips, there are still issues with TSC that
> makes it unusable as a default timecounter.

I think newer chipsets are more liketly to have unusable TSCs. Anything
with power control is unleky to have an almost-constant frequency.

Bruce


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