New port: pvrxxx for Hauppauge PVR150/500

[Ian Smith]

On Mon, 16 Oct 2006, Rick C. Petty wrote:

 > On Mon, Oct 16, 2006 at 05:52:21PM +1000, Ian Smith wrote:
 > > 
 > > Even bit-banging, I expect that it should be able to service interrupts
 > > between bytes - though not between bits, obviously - at least while
 > 
 > Why obviously?  There's a clock line, so I can't see why pausing even
 > between the bits would hurt anything...  so long as your transfer rate is
 > below the 400 kbit/s throughput.  I've done a lot of Atmel AVR i2c myself,
 > even with direct bit-banging it seems to work just fine.  Of course, if you
 > could offload the bus timing you would see a huge performance gain, but
 > that's not possible AFAIK in this case.

Looking at the I2C timing diagrams, I suspect you may be right, though
you'd likely only want to stretch timing with SCL high (ie not mid-bit).
Also, while the master controls SCL, the slave may or may not delay the
clock on acknowledge; I think dealing with it bytewise would be simpler.

Anyway, just in addressing this nasty 20-plus second delay reported on
loading firmware, enabling interrupts between bytes sounds like much
easier work and would reduce latency to one nine-bit byte-time, or
~22.5uS @400kHz, which surely beats 20 seconds of unresponsiveness :) 

[..]

 > > does appear that iicbb is pretty long in the tooth ('98?)
 > 
 > The iicbb could use some cleaning up.  I could take a look at it if no one
 > else has the time/ability.

It sure won't be me, on either count .. back to AVR bit-twiddling ..

Cheers, Ian