Pruning Redux

[Kurt Lidl]

Warner Losh writes:

> I've removed the SMP versions of the Ingenic JZ4280 config files. This is
> the CI20 board(s), but not the ones based on X1000 which are not SMP.
> Rather than removing the port as initially discussed, I took this more
> limited action.

[...]

> I've also implemented the atomic_swap_64 in a less optimal, but more
> portable, way. I hope to circulate it for testing shortly. At that time,
> the old CI20 config files will really break, but I thought it best to
> communicate and document this happening in advance of it really happening.
> Once *that* is in the tree, I'll go remove all the hacks we have in place
> because mips didn't have the proper 64-bit ops.

I looked into this a little, mostly just from a curiosity standpoint.  I 
most explicitly don't disagree with any of the actions that were taken.

So in my examination of the situation, I see that in the mips32r6 
instruction set (which the MZ4280 implements), there are two new 
instructions:

     LLWP - load linked word paired
     LLWPE - load lined word paired EVA

These instructions can be used to atomically load two 32 bit quantities 
into two registers.  There are certain caveats about the memory from 
which they are loaded must be synchronizable between all CPU cores and 
all I/O devices, but I don't think that this would be a problem for our 
intended use case.

Similarly, the 'SC' (store conditional word) instruction, can, in a 
loop, be used to atomically store two 32bit quantities into memory. 
(See example code on page 350 of the 'The MIPS Instruction Set v6.06' 
pdf file.)

Is there some reason these instruction could not be used to implement 
the missing 64bit atomic functions for mips32?  Yes, it would mean that 
this would raise the minimum MIPS ISA for 32-bit SMP would jump to 
mips32r6, but that might be better than no support at all.  For 
uniprocessor support, I think whatever the reworked code from Warner is 
probably the correct forward path to take.

-Kurt