[Differential] [Closed] D5078: Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for clearing hazards

[adrian (Adrian Chadd)]

This revision was automatically updated to reflect the committed changes.
Closed by commit rS295150: Move MIPS32 Release 2 and Release 3 CPUs to use the EHB instruction for (authored by adrian).

CHANGED PRIOR TO COMMIT
  https://reviews.freebsd.org/D5078?vs=12746&id=12956#toc

REPOSITORY
  rS FreeBSD src repository

CHANGES SINCE LAST UPDATE
  https://reviews.freebsd.org/D5078?vs=12746&id=12956

REVISION DETAIL
  https://reviews.freebsd.org/D5078

AFFECTED FILES
  head/sys/mips/include/cpuregs.h

CHANGE DETAILS
  diff --git a/head/sys/mips/include/cpuregs.h b/head/sys/mips/include/cpuregs.h
  --- a/head/sys/mips/include/cpuregs.h
  +++ b/head/sys/mips/include/cpuregs.h
  @@ -110,6 +110,7 @@
    *	C:	Cacheable, coherency unspecified.
    *	CNC:	Cacheable non-coherent.
    *	CC:	Cacheable coherent.
  + *	CCS:	Cacheable coherent, shared read.
    *	CCE:	Cacheable coherent, exclusive read.
    *	CCEW:	Cacheable coherent, exclusive write.
    *	CCUOW:	Cacheable coherent, update on write.
  @@ -154,9 +155,20 @@
   #define	MIPS_CCA_CACHED		0x03
   #endif
   
  -#if defined(CPU_MIPS1004K)
  -#define	MIPS_CCA_UNCACHED	0x02
  -#define	MIPS_CCA_CACHED		0x05
  +/*
  + * 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support
  + * Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent
  + * CCA 0x03 and Uncached Accelerated CCA 0x07
  + */
  +#if defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) ||	\
  +    defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV)
  +#define	MIPS_CCA_CNC		0x03
  +#define	MIPS_CCA_CCE		0x04
  +#define	MIPS_CCA_CCS		0x05
  +#define	MIPS_CCA_UA		0x07
  +
  +/* We use shared read CCA for CACHED CCA */
  +#define	MIPS_CCA_CACHED		MIPS_CCA_CCS
   #endif
   
   #ifndef	MIPS_CCA_UNCACHED
  @@ -214,8 +226,18 @@
   #define	COP0_SYNC	.word 0xc0	/* ehb */
   #elif defined(CPU_SB1)
   #define COP0_SYNC  ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
  -#elif defined(CPU_MIPS74K) || defined(CPU_MIPS1004K)
  -#define	COP0_SYNC	 .word 0xc0	/* ehb */
  +#elif defined(CPU_MIPS24K) || defined(CPU_MIPS34K) ||		\
  +      defined(CPU_MIPS74K) || defined(CPU_MIPS1004K)  ||	\
  +      defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) ||	\
  +      defined(CPU_PROAPTIV)
  +/*
  + * According to MIPS32tm Architecture for Programmers, Vol.II, rev. 2.00:
  + * "As EHB becomes standard in MIPS implementations, the previous SSNOPs can be
  + *  removed, leaving only the EHB".
  + * Also, all MIPS32 Release 2 implementations have the EHB instruction, which
  + * resolves all execution hazards. The same goes for MIPS32 Release 3.
  + */
  +#define	COP0_SYNC	.word 0xc0	/* ehb */
   #else
   /*
    * Pick a reasonable default based on the "typical" spacing described in the

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To: Sgalabov_gmail.com, MIPS, adrian, imp
Cc: freebsd-mips-list
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