[RFC] Cache control from user land (patch)

[Sean Bruno]

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On 01/13/15 11:06, sson wrote:
> Hi all:
> 
> Below is a link to a patch that provides a sysarch() so that cache
> lines may be invalidated from userspace (via the sysarch() system
> call).   For convenience mips_cacheflush() is provided in the
> machine/cachectl.h header file:
> 
> int mips_cacheflush(void *addr, size_t nbytes, int whichcache);
> 
> mips_cacheflush() flushes the content of the selected cache for the
> user addresses in the range from addr to (addr+nbytes-1).
> whichcache may be:
> 
> MIPS_CF_ICACHE:   Flush the instruction cache lines for a given
> user address range. MIPS_CF_DCACHE:  Write back to memory and
> invalidate the cache lines for a given user address range. 
> MIPS_CF_BCACHE:  Write back and invalidate both types of caches for
> a given user address range. MIPS_CF_ICACHE_ALL, MIPS_CF_DCACHE, or
> MIPS_CF_BCACHE: Full the entire given cache(s).
> 
> mips_cacheflush() may return the errno EFAULT or EINVAL (whichcache
> is not valid).  In short, it is similar to the cacheflush() that
> netbsd provides for mips.
> 
> The diff: 
> https://people.freebsd.org/~sson/mips/cacheflush/mips_cacheflush.diff
>
>  Comments, concerns, questions, suggestions, etc. are welcome.
> 
> Regards,
> 
> -stacey.
> 
> 
> 
> 
I've tried applying this to head.

I get a reject from the last bits to sys/mips/mips/sys_machdep.c

% cat sys/mips/mips/sys_machdep.c.rej.orig
@@ -39,6 +39,8 @@
 #include <sys/syscall.h>
 #include <sys/sysent.h>

+#include <machine/cache.h>
+#include <machine/cachectl.h>
 #include <machine/cpufunc.h>
 #include <machine/cpuinfo.h>
 #include <machine/sysarch.h>
@@ -63,9 +115,6 @@
 		 * update it as well.  Add the TLS and TCB offsets so the
 		 * value in this register is adjusted like in the case of the
 		 * rdhwr trap() instruction handler.
- -		 *
- -		 * XXXSS For more information why this offset is required see:
- -		 * 	'git show c6be4f4d2d1b71c04de5d3bbb6933ce2dbcdb317'
 		 */
 		if (cpuinfo.userlocal_reg == true) {
 #if defined(__mips_n64) && defined(COMPAT_FREEBSD32)
@@ -94,6 +143,8 @@
 	case CHERI_SET_STACK:
 		return (cheri_sysarch_setstack(td, uap));
 #endif
+	case MIPS_CACHEFLUSH:
+		return (mips_sysarch_cacheflush(td, uap));

 	default:
 		break;


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