RFC: figuring out bus behaviour on these mips32r2 chips

[Adrian Chadd]

Hi,

I found that the new QCA955x chip (and some of the QCA934x things in
shipping products versus what I have on my desk at home) behave poorly
unless I do ye olde "write to register; read from register to flush"
paradigm.

In this specific instance, it's the MDIO controller on each MAC - if I
do a read-after-write to those registers, everything is peachy.
Without it - and even with a call to wmb() - it still barfs.

Now, I went digging through the mips code, and wmb() -> mips_sync() ->
just a sync operation. It doesn't do any other kind of barrier.

So - what's the mips32r2 spec require us to do for ensuring device IO
has made it out to devices and we enforce ordering? Are we missing
something in our mips_sync() implementation?



-adrian