CACHE_LINE_SIZE macro.

[Stanislav Sedov]

On Nov 5, 2012, at 8:49 AM, Warner Losh <imp at bsdimp.com> wrote:
> 
> Is that an out-of-kernel interface?
> 
> If we did that, we'd have to make it run-time settable, because there's no one right answer for arm and MIPS cpus: they are all different.
> 

IIRC, several linux application use getconf to retrieve the host CPU cache line
value at the compile time to use for the alignment.  I don't really like this
solution as it makes the binaries unportable between different CPUs.

OTOH, it looks like at least for ARM all cpus with a certain ARM core share the
same cache line size, and we don't guarantee that e.g. ARMv5 executable will
be able to run on ARMv7 without performance penalty.  So it might be a good
solution for ARM.  I don't know about MIPS though.

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ST4096-RIPE