heads up - ar71xx changes

[Adrian Chadd]

On 4 May 2012 11:30, Patrick Kelsey <kelsey at ieee.org> wrote:

> Hmmm.  On the RB450G, arge1 is connected to port 5 on the AR8316
> switch, and port 5 on the AR8316 is configured by the boot loader to
> bypass the switch complex and connect directly to an internal PHY.
> The MDIO bus on the AR8316 is wired to arge0.  arge0 is connected to
> the cpu port on the AR8316, with no real PHY.  That hack diff I sent
> is making less and less overall sense (although it does let me limp
> along for the moment).
>
> What I really want is for arge0 to initialize to whatever fixed rate
> is hinted (or defaulted when no hint is given), and I want arge1 to
> see its PHY on the MDIO bus attached to arge0.  Perhaps I should have
> ARGE_MDIO defined whereas I currently do not?

Right. this is very much like what my AP96 reference board has.

The previous code had a hack which was only valid for AR71xx/AR913x,
where it assumed arge0 and arge1 miibus were the same - it just used
the arge0 MDIO lines. There was no "arge1 MDIO" interface. The AR724x
and later SoCs can have 2 MDIO busses.

I've "solved" this by using the arge mdio/mii bus split code from
stefan, which is in -HEAD. It's a bit of a round about way of
specifying mdio and mii busses, but it lets you (later) do weird and
wonderful things, like hang an MII bus off of something internal to a
switch, so you can hang ukphy or whatever other PHYs off of it.

You could look at the AP96 and AP96.hints files in sys/mips/conf/ and
see if my arge0/arge1 hints work for you.

What _I_ should do is grab that switch driver and see if it works for
me. If it does, I may just commit it to -HEAD as a starting point for
the switch API that ray@ has been working on, and then bring over his
switch API. That at least lets me get AR71xx + AR8316 support for the
AP96 and Routerstation Pro boards, and gives me a starting point to do
further testing/development with.

Thanks!



Adrian