Merging 64 bit changes to -HEAD

[Jayachandran C.]

On Tue, Jun 29, 2010 at 2:28 AM, Luiz Otavio O Souza <lists.br at gmail.com> wrote:
>> Thanks for the the update. Looks like pmap_map for kernel is failing,
>> may be the new tlb_update code causes this.  Can you apply the
>> attached patch and see if the problem still persists, it replaces the
>> new tlb_update code with the older version.
>>
>> Obviously not a fix, but if we can narrow it down to this function,
>> fixing will be easier.
>>
>> JC.
>> <try.diff>
>
> JC,
>
> This fix the problem ! Thanks ! Now, at least, you know where to look :)

The new tlb_update does not seem to update the tlb entry if the tlbp
fails.  Here's a patch that should make the new function behave like
the older one.  The patch is in attached file 'tlb-update.diff'.

If that does not work, I'm not sure what the issue is.  You could also
try try the nop-change.diff attached. It tries to switch the ssnop
used for delay in the new code with 'nop' which was used by the old
code.

Thanks,
JC.
-------------- next part --------------
Index: sys/mips/mips/tlb.c
===================================================================
--- sys/mips/mips/tlb.c	(revision 209521)
+++ sys/mips/mips/tlb.c	(working copy)
@@ -217,19 +217,21 @@
 void
 tlb_update(struct pmap *pmap, vm_offset_t va, pt_entry_t pte)
 {
-	register_t mask, asid;
-	register_t s;
+	pt_entry_t other;
+	register_t mask, asid, hi, s;
 	int i;
 
 	va &= ~PAGE_MASK;
+	other = pte & PTE_G;
 	pte &= ~TLBLO_SWBITS_MASK;
+	hi = TLBHI_ENTRY(va, pmap_asid(pmap));
 
 	s = intr_disable();
 	mask = mips_rd_pagemask();
 	asid = mips_rd_entryhi() & TLBHI_ASID_MASK;
 
 	mips_wr_pagemask(0);
-	mips_wr_entryhi(TLBHI_ENTRY(va, pmap_asid(pmap)));
+	mips_wr_entryhi(hi);
 	tlb_probe();
 	i = mips_rd_index();
 	if (i >= 0) {
@@ -241,6 +243,17 @@
 			mips_wr_entrylo1(pte);
 		}
 		tlb_write_indexed();
+	} else {
+		mips_wr_pagemask(0);
+		mips_wr_entryhi(hi);
+		if ((va & PAGE_SIZE) == 0) {
+			mips_wr_entrylo0(pte);
+			mips_wr_entrylo1(other);
+		} else {
+			mips_wr_entrylo0(other);
+			mips_wr_entrylo1(pte);
+		}
+		tlb_write_random();
 	}
 
 	mips_wr_entryhi(asid);
-------------- next part --------------
Index: sys/mips/include/cpuregs.h
===================================================================
--- sys/mips/include/cpuregs.h	(revision 209521)
+++ sys/mips/include/cpuregs.h	(working copy)
@@ -119,7 +119,7 @@
  * Pick a reasonable default based on the "typical" spacing described in the
  * "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
  */
-#define	COP0_SYNC  ssnop; ssnop; ssnop; ssnop; ssnop
+#define	COP0_SYNC  nop; nop; nop; nop; nop
 #endif
 #define	COP0_HAZARD_FPUENABLE	nop; nop; nop; nop;