[RFC] Event timers on MIPS

[Neel Natu]

Hi Alexander,

Your patch works fine on a Sibyte. I verified that wall clock time is
progressing as expected. Is there any other test that you recommend?

I have a few comments about the patch:

1. set_cputicker() in clock_attach() should be moved back up to
    mips_timer_init_params(). Otherwise the platform-specific CPU tickers
   used by Sibyte, Octeon and RMI will be overwritten by the mips32 ticker.

2. The local variable 'cycles_per_tick' in clock_intr() can now be a uint32_t.

3. Is there a race between setting 'cycles_per_tick' in clock_start() and
    clock_intr()? Would it be better to write the compare register first
    and then set 'cycles_per_tick' to a non-zero value?

    If I understand the code correctly we are liable to get clock interrupts
    even afer the clock is stopped when the CP0 COUNT register matches
    0xffffffff.

4. We need to update the DPCPU(compare_ticks) value when we start the timer
    in clock_start().

5. I think the entire 'lost_ticks' processing in clock_intr() should be
    conditional on (cycles_per_tick > 0). Without this we may incorrectly
    update the value of DPCPU(lost_ticks).

6. Can you a couple of lines of explaining the computatation of
    'et_min_period' and 'et_max_period'? It is not completely obvious to me.

best
Neel

2010/7/20 Alexander Motin <mav at freebsd.org>:
> Alexander Motin wrote:
>> I've made a patch, updating MIPS timer code (except RMI) to utilize new
>> MI event timer infrastructure. I've successfully built QEMU and XLR
>> kernels with the patch. Unluckily I can't test how it works, unless
>> somebody teach me how to cook QEMU to run it. I also haven't ported RMI
>> timers drivers, as I am not sure how that hardware is intended to work.
>>
>> Patch for HEAD can be found here:
>> http://people.freebsd.org/~mav/timers_mips.patch
>
> Slightly updated version for fresh HEAD:
> http://people.freebsd.org/~mav/timers_mips2.patch
>
> --
> Alexander Motin
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