[RFC] Event timers on MIPS

[Alexander Motin]

M. Warner Losh wrote:
> In message: <4C41A248.8090605 at FreeBSD.org>
>             Alexander Motin <mav at FreeBSD.org> writes:
> : I've made a patch, updating MIPS timer code (except RMI) to utilize new
> : MI event timer infrastructure. I've successfully built QEMU and XLR
> : kernels with the patch. Unluckily I can't test how it works, unless
> : somebody teach me how to cook QEMU to run it. I also haven't ported RMI
> : timers drivers, as I am not sure how that hardware is intended to work.
> : 
> : Patch for HEAD can be found here:
> : http://people.freebsd.org/~mav/timers_mips.patch
> 
> I'll have to take a look at things.  On MIPS, the COMPARE register is
> per core, so you don't need to send an IPI if you are using that
> hardware.  IPIs are a little expensive, IIRC, since they tend to have
> bad cache effects and put extra pressure on the TLBs.
> 
> It wasn't clear from these patches if you are using one core to do the
> signalling for all the others or not.  If so, that represents a bit of
> a regression.  I'm also not sure about not having a per-cpu timer's
> effect on performance on a 16 or 32 core MIPS box...

I am registering event timer as per-CPU:
+	sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
+	    ET_FLAGS_PERCPU;

Clock IPI's added only for completeness, in case there will be supported
any other non-per-CPU timers, like mentioned PIC clock on XLR.

Thanks.

-- 
Alexander Motin