SMP support for n64 patch.

[Jayachandran C.]

On Thu, Aug 12, 2010 at 12:31 PM, M. Warner Losh <imp at bsdimp.com> wrote:
> In message: <AANLkTimQVoRTc3CHNGHNAS2-PRqiZ8BiStekp6tj1Qc4 at mail.gmail.com>
>            "Jayachandran C." <c.jayachandran at gmail.com> writes:
> : I've attached a patch that enables SMP support for N64 builds (I can
> : get XLR come up multi-user with 32 cpus with this).
> :
> : I ended up making KX bit in status register set when you are in
> : userspace, since the PCPU area is now mapped in XKSEG.  The PCPU area
> : needs to be accessed in  I have reverted the earlier change that
> : enabled KX on kernel entry from userspace since that is no longer
> : needed.
> :
> : Please let me know your comments.
>
> If I understand correctly, and I'm sure the pedants will tell me
> otherwise, the KX bit means that a legal reference to a kernel address
> is made, it will be interpreted as a 64-bit address when KX is set,
> and a 32-bit address when it is clear.
>
> It does not grant any additional access to the kernel memory that
> isn't already granted by the TLB entries, correct?  It doesn't grant
> access to the kernel memory, correct?

My understanding is this, but I was not able to find any reference
that says exactly that (so was not sure if some MIPS implementations
have issues here).

> But I'm a little confused.  I'm reading through section 4.5 of the
> Privileged Resources Architecture document from mips
> (MD00091-2B-MIPS74PRA-AFP-02.50.pdf) and table 4-1 suggests that
> running with it in user mode won't change what can be accessed.  So
> why would it need to be turned on at all in user mode?  Rather than
> the xtlb routine being called for the refill for a kernel address, it
> will fault instead.
>
> Or is this an optimization for the xtlb handler which needs to get to
> pcpu data?

Yes, otherwise I need to add code to the XTLB handler to enable KX
(which will involve read and write to status register and the related
hazards).  Enabling KX everywhere, including userspace avoids this.

JC.