SMP support for XLR processors.

[Neel Natu]

Hi JC,

On Sat, Apr 17, 2010 at 3:40 PM, C. Jayachandran
<c.jayachandran at gmail.com> wrote:
> I've a set of initial patches to enable SMP for RMI processors. It
> comes up in multi-user with 32 CPUs.  I could do buildworld before I
> updated to HEAD - with head there is a hang during buildworld which
> I'm looking at, but I think the initial work can be checked in.
>
> Neel, can you have a look at the first two patches - one is to enable
> ULE scheduler and the second one is to move platform_init_ap to
> slightly later in the initialization sequence.
>
> The patches are :
> 1. mips-ule-support.patch
> - Enable ULE scheduler for MIPS
>
> 2. mips-smp-move-platform.patch
> - We need a hook to setup message ring and its interrupts, we use
> platform_init_ap now, and move it be called later for XLR
>

I would like to see us move away from #ifdef TARGET_FOO in files under
mips/mips as much as possible. I think that is achieved easily in this
instance.

How about we create a function platform_ap_enable_interrupts() that is
called from smp_init_secondary()? This function will be defined for
each platform.

In the common case this function will simply call
mips_ap_enable_interrupts() that encapsulates the logic that we
currently have to setup interrupt masks for clock and ipi interrupts
in the status register. In the XLR case however it can do something
different.

Ditto about the #ifdef TARGET_XLR_XLS in mpboot.S. You can simply have
an empty platform_init_ap() for XLR.

best
Neel

> 3. rmi-prid.patch
> Add RMI processor ID prints - right now it prints unknown processor.
>
> 4. rmi-pcib-fix.patch
> XLR pci bridge should be off the IODI bus, currently it is off the
> nexus bus which will cause issue when bus_setup_intr on nexus is
> called
>
> 5. cleanup-reorg-cpuid-rge-kx.patch
> This set has a many changes rolled up:
>  - clean up rge driver, remove unused code paths and commented code
> (long way to go still)
>  - xlr_cpu_id(), xlr_core_id() and xlr_thr_id() updated and usage updated
>  - fix a bug - we cannot use MIPS_PHYS_TO_KSEG0 on physical addresses
> here, I have made changes for using XKPHYS to do the same process.
>  - the KX bit is enabled and interrupts are disabled before the
> physical memory is read, to avoid the KX bit setting from affecting
> other code.
> - move message ring code to on_chip.c from xlr_machdep.c, now all
> message ring code is in on_chip.c
>
> 6. rmi-xlr-smp.patch
> SMP Support for XLR
> - mpwait.S added to get the other CPUs out of bootloader code at startup.
> - SMP platform related functions.
> - disable shared TLB code for SMP - since threads have different mappings.
>
> The patches are also available at
> http://sites.google.com/site/cjayachandran/files
>
> Enabling all 32 threads will need a minor fix in the SMP code, see the
> patch subr_smp-fix.patch at the same place.
>
> Regards,
> JC.
>