Broadcom MIPS progress

[Bruce M. Simpson]

Bruce M. Simpson wrote:
>
> I am now scratching my head over how to attach child devices.

This is kinda worked out, I now have newbus style children probing and 
trying to attach. This is cool, it means probe routines can be written 
in much the same way as for PCI; the siba bus driver will enumerate the 
bus, set vendor/device IDs in a devinfo structure, and export them to 
potential children via accessors just like pci(4) does.

%%%
siba0: <Sonics SiliconBackplane rev 2.3> at mem 0x18000000-0x18006fff on 
nexus0
siba_attach: entry
nexus_release_resource: entry
siba_cc0 on siba0
siba_alloc_resource: entry
siba_cc0: unable to allocate memory
device_attach: siba_cc0 attach returned 6
siba0: <0x4243, 0x0806 "Ethernet core"> not attached
siba0: <0x4243, 0x080b "IPSEC accelerator"> not attached
siba0: <0x4243, 0x0808 "USB host controller"> not attached
siba_pcib0 on siba0
siba_alloc_resource: entry
siba_pcib0: unable to allocate memory
device_attach: siba_pcib0 attach returned 6
siba_mips0 on siba0
siba_alloc_resource: entry
siba_mips0: unable to allocate memory
device_attach: siba_mips0 attach returned 6
siba_sdram0 on siba0
siba_alloc_resource: entry
siba_sdram0: unable to allocate memory
device_attach: siba_sdram0 attach returned 6
%%%

I just need to work out the kinks with resource allocation; siba will 
need to export a resource manager to its direct children for 
configuration space which it has already reserved, and proxy the 
allocations for bus space outside its own range further up.

>
> It seems likely that a full pci-style bus implementation will be 
> needed in siba (instance variables, devinfo etc) as it is likely that 
> architecture-independent code can be reused; in particular, ubsec(4), 
> uart(4) and bfe(4) for the onboard devices. I believe the onboard USB 
> host controller is OHCI. 


It looks as though this stuff is beginning to come together. I'd aim 
next to flesh out the basic ChipCommon functionality, determining the 
board clocks, setting up the UARTs and hooking them up to uart(4). Then, 
interrupt routing.

After that stuff like bfe(4) can be dealt with. The OHCI controller on 
the WGT634U is not pinned out, there is a separate EHCI controller on 
the PCI bus to implement USB2.

I believe the 4710 based systems are also using Siba so running on the 
WRT54G/S and WL-HDD2.5 should be feasible once we get bfe(4) hooked up 
to siba and stuff like ethercons is possible (as these systems have no 
UART which can be used for debugging the kernel during bringup, and 
their PMON firmware is primitive compared to CFE).

Finally, getting the pci host bridge will be needed to access the 
Atheros 5213 MiniPCI card which ships in the WGT634U's PCI slot.

Regards,
BMS