IRQ31 and IRQ32 on HPDL585 running FreeBSD 7.0 are consuming HIGH CPU usage

[John Baldwin]

On Thursday 13 November 2008 03:19:36 am Jeremy Chadwick wrote:
> On Thu, Nov 13, 2008 at 12:07:37AM -0800, Won De Erick wrote:
> > Noted on this, I will update you through this thread.
> > 
> > However is there any possibility of the following:
> > 
> > > I don't know if there's a way to split the interrupt request for each 
bce's Rx and Tx,
> > > which means a total of four IRQs, and eventually four cores (or 4 CPUs)
> > > for the transactions. With this way, the IDLE processors would be 
utilized.
> > 
> > What I mean here is, for the two interfaces:
> > 
> > one IRQ for bce0 Rx
> > one IRQ for bce0 Tx
> > one IRQ for bce1 Rx
> > one IRQ for bce1 Tx
> 
> I can't even begin to imagine how this would be possible on any NIC.

igb(4) does it.  It is quite possible and one of the purposes of MSI.  
However, the current bce(4) hardware does not support this.  It only allows 
for a single message and thus a single IRQ per-device.

-- 
John Baldwin