PCI speed

[Andrew Gallatin]

On 03/03/2017 17:34, Dirk-Willem van Gulik wrote:
> Forgive me my ignorance - but for some cards - pciconf(8) nicely lists the speed of the bus:
>
>> ciss0 at pci0:12:0:0:      class=0x010400 card=0x3243103c chip=0x323a103c rev=0x01 hdr=0x00
> ...
>>     cap 10[70] = PCI-Express 2 endpoint max data 128(256) RO NS
>>                  link x4(x8) speed 5.0(5.0)
>>     cap 11[ac] = MSI-X supports 16 messages, enabled
>>                  Table in map 0x10[0x1c2000], PBA in map 0x10[0x1c4000]
>>   PCI-e errors = Correctable Error Detected
>>                  Fatal Error Detected
>>                  Unsupported Request Detected
>
> and that matches exactly with what it is. While for other cards it does not seem to report that:
>
>> mpt4 at pci0:7:8:1:        class=0x010000 card=0x10b01000 chip=0x00301000 rev=0x08 hdr=0x00
> ....
>>     cap 01[50] = powerspec 2  supports D0 D1 D2 D3  current D0
>>     cap 05[58] = MSI supports 1 message, 64 bit
>>     cap 07[68] = PCI-X 64-bit supports 133MHz, 2048 burst read, 8 split transactions
>>     cap 00[70] = unknown
>
> and in fact seems to mis report the bus - this is a  PCIe Gen 2 x4 bus with a x8 Connector Width
> holding  a LSI 22320SE Ultra320 SCSI dual channel PCIe X4 card.
>
> How should one interpret this ?
>
> Dw.
>
>

The mpt seems to be a PCI-X device, not a PCI Express device.  So it
is likely that the add-on card actually contains a PCI-e to PCI-X
bridge chip.

PCI Express was *very* hard to get right in the early days of Gen 1
before companies had built up large PCIe IP libraries and test suites.
So a lot of companies with existing PCI and PCI-X products shipped
"native" PCIe products that were actually composed of a PCIe connector
with a third part PCIe to PCI-X bridge.

It might be interesting to see what's upstream from the bus.  I'd
expect there is a PLX (or maybe IDT) device in there.

Drew