I/O-APIC redirection table on AMD chipsets

[Andriy Gapon]

I just want to share a small discovery.

For AMD SB7x0 and SB8x0 southbridges (and maybe the newer chipsets too) the
Delivery Mode bits in the IO-APIC redirection table MUST be programmed according
to the HyperTransport specification, NOT the APIC specification and chipset
documentations.

For example, for NMIs the delivery mode has to be set to 3 (011b).
BTW, the HyperTransport specification says that the destination ID should be
0xff (broadcast) for the NMI type, but in my tests it can be an individual APIC
ID as well.

Fixed, Lowest Priority and SMI modes have the same encoding in both
specification.  That explains why this peculiarity is not well known.

Refer to Appendix F.1 of the HyperTransport 3.0 Specification for x86 interrupt
delivery modes.
-- 
Andriy Gapon