instability of timekeeping

[Andriy Gapon]

On 27/10/2015 13:58, Konstantin Belousov wrote:
> On Tue, Oct 27, 2015 at 11:04:47AM +0200, Andriy Gapon wrote:
>> And now another observation. I have C1E option enabled in BIOS. It
>> means that if all cores enter C1 state, then the whole processor
>> is magically placed into a deep C-state (C3, I think). LAPIC timer
>> on this CPU model does not run in the deep C-state. So, I had to
>> disable C1E option to test the LAPIC timer in a useful way. But
>> before actually testing it I first tried to reproduce the problem. As
>> you might have already guessed the problem is gone with that option
>> disabled. Scratching my head to understand the implications of this
>> observation.
> 
> Most obvious explanation would be that the latency of wakeup is very large.
> What is the HPET frequency when the jitter occur ?
> 

kern.timecounter.tc.TSC-low.frequency: 1607351869
kern.eventtimer.et.HPET.frequency: 14318180

Or did you mean the actual rate of timer interrupts?

-- 
Andriy Gapon