PMCSTAT Event for counting L1-DCache Hit / Misses

[Sai Prajeeth]

Intel Xeon X5650 2660.05-MHz K8-class CPU. Family = 0x6  Model = 0x2c
 Stepping = 2.

Pretty sure its Intel Nehalem architecture.


On Thu, Jun 18, 2015 at 12:37 AM, Ryan Stone <rysto32 at gmail.com> wrote:

> On Mon, Jun 15, 2015 at 1:48 PM, Sai Prajeeth <csprajeeth at gmail.com>
> wrote:
>
>> Hi,
>>
>> I am not able to find the event that counts the L1 Data cache hits and
>> misses in pmccontrol -L. Can anyone tell me what the events are so that i
>> can get the counts using pmcstat ?\
>>
>> Thanks!
>>
>
> This is specific to your processor model (not just amd64 or armv7, but the
> model name like "Sandy Bridge" or "Intel E5-2600").  What processor model
> do you have?  It's printed to dmesg and /var/log/messages during boot.
>