atomic_load_acq @ i386/amd64

[Konstantin Belousov]

On Sat, Jan 04, 2014 at 12:51:59AM +0400, Oleg Bulyzhin wrote:
> 
> Hello.
> 
> I've got a question: why atomic_load_acq_* implemented on i386/amd64 archs
> with locked cmpxchg instruction? Comment about this
> (in /sys/(amd64|i386)/include/atomic.h) looks wrong for me. I believe
> acquire/release semantics does not require StoreLoad barrier so simple aligned
> load should be enough. (because acquire/release semantics does not guarantee
> sequential consistency).

You did not explicitely wrote which statement in the comment is false, in
your opinion.

FreeBSD assumes a property of _acq/_rel stuff which is sometimes called
'total lock ordering'. It is indeed sort of sequential consistency, but
only for atomic+membar ops. Would atomic_load_acq()  implemented as plain
load, it can pass stores, in particular stores from the _rel op, which
breaks the guarantee.

For x86, there are indeed two possible schemes for implementing critical
section, one is lock cmpxchg for get(), and plain store for release(),
which is what we use. Another is plain load for get(), and xchg for
release().  Then, the load_acq() must be adopted to not break the acq/rel
consistency, and since we use plain store for release(), load_acq must
use serialing instruction.
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