MIPS: bus_dma(9) and cache problems

[Jason Harmening]

>     1. code modifies data in block and this modification ends up in
>        cache and is not written back to memory
>     2. right after this code calls bus_dmamap_sync for this buffer
>        and as a result cache invalidation is performed
>     3. Cache function operates on cache line size-aligned addresses
>        and the block in question happens to share the same cache line
>        with the buffer. So modification made at step (1) is lost.

What sync operation are you doing?  At least for PREREAD or PREWRITE,
I'd expect any dirty cache lines to be flushed to RAM.  If this isn't
happening, then you may want to submit a bug report.

BTW, if you haven't already found it the MIPS sync code for 9-CURRENT is here:

http://fxr.watson.org/fxr/source/mips/mips/busdma_machdep.c#L760