MIPS: bus_dma(9) and cache problems
gonzo at bluezbox.com
Tue Oct 27 00:26:31 UTC 2009
This problem haunts for a couple of days and I can't find a
nice and clean solution so this email is actually a cry for help.
There is a buffer loaded by bus_dmamap_load for use as a
DMA buffer. Right before this buffer resides block of vital
data structure. Consider following scenario:
1. code modifies data in block and this modification ends up in
cache and is not written back to memory
2. right after this code calls bus_dmamap_sync for this buffer
and as a result cache invalidation is performed
3. Cache function operates on cache line size-aligned addresses
and the block in question happens to share the same cache line
with the buffer. So modification made at step (1) is lost.
If busdma code controls allocation (bus_dmamem_alloc) this situation
can be avoided by forcing pointer alignment. But when address come
from the "outer space" via bus_dmamap_load* there is not much to do.
There are two solutions I've figured so far:
- Create bounce page for not properly aligned memory. Which would
reduce performance a lot.
- Remap buffer's page(s) as uncached. I haven't succeeded with this
one yet and not sure it's always possible.
May be someone can suggest better way to clean this mess?
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