AMD SB700 SMBus controller driver

[Andriy Gapon]

According to SB700 specifications its SMBus controller is very similar to one in
PIIX4.
The differences that I see so far:

1. Interrupt Line/Interrupt Pin PCI configuration registers (0x3c, 0x3d) do not
specify interrupt number that the controller could use:
> This register specifies which interrupt pin the device issue
> This module does not generate interrupt but contains the
> actual interrupt controller. This register is hardcoded to 0.

2. I2CbusConfig register (0xd2) uses bit #1 to indicate whether SMI or regular
interrupt is used in interrupt mode; PIIX4 uses bit 3.

I couldn't get our intpm driver to work with this hardware by simply adding PCI id
and tweaking 0xd2 bits meaning.

I could get it to work by forcing polling mode. It appears that Linux driver for
this HW always uses polling mode, and OpenBSD and NetBSD drivers would use it with
this HW too.

I am still trying to get interrupt mode to work.
I set 0xd2 to enable regular interrupt generation (it is set to SMI after boot).
SB700 specifications say at one place that SMB interrupt is connected to INTIN20
pin of IO-APIC in APIC mode. I tried setting up IRQ20 in the driver but no
interrupts are generated. And there are no stray interrupts either.
So I am not sure - either this HW doesn't generate normal interrupts at all, or
they to a different pin, or additional setup is required, or I am doing something
wrong.

Anyway, I plan to produce an updated version of intpm driver with possibility of
forced or auto-detected polling mode and support for PCI id of SB700 SMBus
controller and its peculiarities.

-- 
Andriy Gapon