Accurate/Fine-grained timing of latency in atheros drivers

Sam Leffler sam at
Fri Jul 1 17:06:02 GMT 2005

Sam Pierson wrote:
> Hey guys,
> In a current project, I need to find out exactly how long it takes to send
> a 802.11 packet and how much time is spent in the following stages:
> send time - time spent constructing message, including context switches
> and other delays and the time it takes to transfer the message to the
> network card.

You didn't provide enough info to really answer this but it sounds like 
it's time spent prior to handing the packet to the h/w in which case you 
need to augment the existing code.  Atheros h/w uses dma so "time it 
takes to transfer the message to the network card" is kinda nebulous. 
If you want to know when the h/w starts dma then you can mark a tx 
descriptor to get an interrupt when it's processed but unless you poll 
the tx dma registers you cannot tell when dma has started and even then 
you can only get an approximation.  The better thing to do is use a bus 
analyzer and watch for particular data patterns and/or addresses.

> access time - delay which we experience waiting to access the transmitting
> channel.  Normally this would include the RTS and CTS queuing signals,
> but for this application, I have to disable them.  Is it possible that no time
> is spent waiting here, if I have disabled the whole CSMA scheme on the
> hardware level?

Depends.  Regardless you'll need to monitor at the h/w level with an 

> propagation time - how long it takes to get to the receiver, once it has left
> our card

You must monitor the medium unless sniffing for the ack is good enough.

> receive time - how long it takes for the receiving network card to get the 
> message and notify the host that it has something to read.

You need h/w monitoring.

> Am I going to have to put in hardware interrupts to time these events or 
> are such tools already available?  

You need to expose the pci bus and use an analyzer for much of this.


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