em0, polling performance, P4 2.8ghz FSB 800mhz

[Luigi Rizzo]

On Wed, Mar 03, 2004 at 10:03:11AM -0500, Andrew Gallatin wrote:
> 
> Don Bowman writes:
> 
>  > I'm not sure what affect on fxp. fxp is inherently limited
>  > by something internal to it, which prevents achieving 
>  > high packet rates. bge is the best chip, but doesn't

but you should not compare apples and oranges. the fxp is a 100mbit NIC,
the bge is a GigE NIC.

> Just curious - why is bge the best chip?  Is it because
> it exports a really nice API (separate recv ring for small messages),
> or is the chip inherently faster, regardless of its API?
> 
> I'm trying to design a new ethernet API for a firmware-based nic,
> and I'm trying to convince a colleague that having separate
> receive rings for small and large frames is a really good thing.

i am actually not very convinced either, unless you are telling me
that there is a way to preserve ordering. Or you'd be in trouble
when, on your busy link, there is a mismatch between user-level and
link-level block sizes.

So, what is your design like, you want to pass the NIC buffers of
2-3 different sizes and let the NIC choose from the most appropriate
pool depending on the incoming frame size, but still return
received frames in a single ring in arrival order ?
This would make sense, but having completely separate rings
(small frames here, large frames there) with no ordering relation
would not.

	cheers
	luigi
> Drew
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