How to map device addresses into user space

[Warner Losh]

On Jan 3, 2013, at 9:00 PM, Dr. Rolf Jansen wrote:

> Am 03.01.2013 um 17:17 schrieb Mehmet Erol Sanliturk:
> 
>> On Thu, Jan 3, 2013 at 8:45 AM, Dr. Rolf Jansen <rj at cyclaero.com> wrote:
>> 
>>> ...
>>> 
>>> I need to map the Base Address Registers into user space memory, in order to pass the BAR's to the National Instruments Drivers Development Kit (NI-DDK). The DDK is a complex set of C++ classes running in user space, that read/write directly from/into the BAR's.
>>> 
>>> The FreeBSD bus_space_* functions are useless in this respect, because the DDK isn't designed that way, I need the BAR addresses mapped into user space.
>>> 
>>> ...
>> 
>> There is the following book:
>> 
>> FreeBSD Device Drivers
>> 
>> Product Details
>> 
>>    Paperback: 352 pages
>>    Publisher: No Starch Press; Original edition (May 7, 2012)
>>    Language: English
>>    ISBN-10: 1593272049
>>    ISBN-13: 978-1593272043
> 
> 
> Mehmet,
> 
> Many thanks for your response.
> 
> I know this book. It suggests accessing the PCI registers using Newbus (Chapter 7). Newbus hides away direct reading/writing to the BAR's, and therefore, Newbus is useless in the given respect.
> 
> Again, I need the exact PCI Base Address Registers directly mapped into user space, so that I can do in my user space measurement controller something like the following:
> 
>  user_space_BAR[0 + funcOffset] &= 0x03;

(1) You could map /dev/mem. Lots of folks do this.
(2) You could put all that code into your driver so you can map a small part of /dev/mem that corresponds to the part of the physical address space your device occupies. You can get that from rman_get_start from the bar resource that you allocate in your driver. This is a little more complicated, but doable. You'll need to make sure to cleanup in the close as well, otherwise bad things will happen.  Get to know sys/vm. You will need to understand the subtle difference between different wiring and mapping.

Note well that this will only work on architectures where bouncing and special MMU/iommu tricks aren't needed.

Warner