Haswell CPU Feature

[Jia-Shiun Li]

On Tue, Jan 6, 2015 at 1:23 PM, Neel Natu <neelnatu at gmail.com> wrote:

> Hi Sean,
>
> On Mon, Jan 5, 2015 at 6:34 PM, Sean Bruno <sbruno at ignoranthack.me> wrote:
> > I'm thinking something like this:
> >
> > Index: sys/x86/x86/identcpu.c
> > ===================================================================
> > - --- sys/x86/x86/identcpu.c    (revision 276729)
> > +++ sys/x86/x86/identcpu.c      (working copy)
> > @@ -781,7 +781,7 @@
> >                                 "\011TM2"       /* Thermal Monitor 2 */
> >                                 "\012SSSE3"     /* SSSE3 */
> >                                 "\013CNXT-ID"   /* L1 context ID
> available */
> > - -                             "\014<b11>"
> > +                               "\014SDBG"      /* IA32_DEBUG_INTERFACE
> debug*/
> >                                 "\015FMA"       /* Fused Multiply Add */
> >                                 "\016CX16"      /* CMPXCHG16B
> Instruction */
> >                                 "\017xTPR"      /* Send Task Priority
> Messages*/
> >
> >
>
> Looks good.
>

Maybe also this for completeness?

# svnlite diff
Index: sys/x86/include/specialreg.h
===================================================================
--- sys/x86/include/specialreg.h        (revision 276737)
+++ sys/x86/include/specialreg.h        (working copy)
@@ -154,6 +154,7 @@
 #define        CPUID2_TM2      0x00000100
 #define        CPUID2_SSSE3    0x00000200
 #define        CPUID2_CNXTID   0x00000400
+#define        CPUID2_SDBG     0x00000800
 #define        CPUID2_FMA      0x00001000
 #define        CPUID2_CX16     0x00002000
 #define        CPUID2_XTPR     0x00004000

-Jia-Shiun