patch: enable MEM_LOAD_UOPS_LLC_HIT_RETIRED on sandy bridge xeon

[Adrian Chadd]

Hi,

This (and maybe more?) events are applicable to both the sandy bridge and
sandy bridge xeon CPUs.

This is from the Intel SDM June 2013 Volume #3.

David/Jim, does this look fine to you?

Thanks,


ndex: sys/dev/hwpmc/hwpmc_core.c
===================================================================
--- sys/dev/hwpmc/hwpmc_core.c  (revision 254263)
+++ sys/dev/hwpmc/hwpmc_core.c  (working copy)
@@ -1541,13 +1541,18 @@
        IAP_F_SBX | IAP_F_IBX | IAP_F_HW),

     IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-       IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
+       IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
+       IAP_F_IBX | IAP_F_HW),
     IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-       IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
+       IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IIAP_F_IB |
+       IAP_F_IBX | IAP_F_HW),
     IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-       IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
+       IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IIAP_F_IB |
+       IAP_F_IBX | IAP_F_HW),
     IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
-       IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_IBX | IAP_F_HW),
+       IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IIAP_F_IB |
+       IAP_F_IBX | IAP_F_HW),
+
     IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 |
        IAP_F_I7 | IAP_F_WM),
     IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E),