memory barriers in bus_dmamap_sync() ?
scottl at samsco.org
Wed Jan 11 15:54:57 UTC 2012
On Jan 10, 2012, at 2:37 PM, Luigi Rizzo wrote:
> I was glancing through manpages and implementations of bus_dma(9)
> and i am a bit unclear on what this API (in particular, bus_dmamap_sync() )
> does in terms of memory barriers.
> I see that the x86/amd64 and ia64 code only does the bounce buffers.
> The mips seems to do some coherency-related calls.
> How do we guarantee, say, that a recently built packet is
> to memory before issuing the tx command to the NIC ?
In short, i386 and amd64 architectures do bus snooping between the cpu cache and the memory and bus controllers, and coherency is implicit and guaranteed. No explicit barriers or flushes are needed for device mastered DMA. Other CPU architectures have appropriate cache flushes and memory barriers built into their busdma implementations. Note that this is a different scenario than device register accesses, which is essentially host mastered DMA.
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