memory barriers in bus_dmamap_sync() ?

[Luigi Rizzo]

I was glancing through manpages and implementations of bus_dma(9)
and i am a bit unclear on what this API (in particular, bus_dmamap_sync() )
does in terms of memory barriers.

I see that the x86/amd64 and ia64 code only does the bounce buffers.
The mips seems to do some coherency-related calls.

How do we guarantee, say, that a recently built packet is
to memory before issuing the tx command to the NIC ?

cheers
luigi