ticso at cicely7.cicely.de
Thu Sep 4 01:55:16 UTC 2008
On Thu, Sep 04, 2008 at 01:46:42AM +0200, Bernd Walter wrote:
> On Wed, Sep 03, 2008 at 09:47:59PM +0100, David Malone wrote:
> > On Wed, Sep 03, 2008 at 05:49:44AM +0200, Bernd Walter wrote:
> > > Some boards (including my Intel DG33BU) seem to have problems setting
> > > up the mtrr to cache all RAM.
> > > My system runs fast with 2G and ist about 6 times slower in buildworld
> > > with 6G RAM.
> > > I will try a BIOS update once Intels tells me why their update ISO
> > > just turn the system off instead of updating the BIOS - sigh.
> > > But it seems that Linux is doing some kind of fixup for MTRR:
> > > http://lkml.org/lkml/2008/1/18/170
> > > Can we do something similar?
> > You may be able to fix this by just using the memcontrol command -
> > it already lets you program the MTRRs.
> Oh damn - a new fancy tool to play with ;-)
> Interesting - the values look good:
> 0x0/0x80000000 ticso write-back active
> 0x80000000/0x40000000 ticso write-back active
> 0xc0000000/0x10000000 ticso write-back active
> 0xcf800000/0x800000 BIOS uncacheable set-by-firmware active
> 0xcf400000/0x400000 BIOS uncacheable set-by-firmware active
> 0x100000000/0x80000000 ticso write-back active
> 0x180000000/0x20000000 ticso write-back active
> 0x0/0x1000000000 - uncacheable
Ok - there it is - something is missing:
I/O memory addresses:
ram goes up to 0x1abffffff mtrr just goes up to 0x1a0000000 - 1, so the
last 192MB are uncached.
But memcontrol complains when trying to add the range:
cicely14# memcontrol set -b 0x1a0000000 -l 0xc000000 -o ticso write-back
memcontrol: can't set range: Invalid argument
> I've already overwritten it for tests, but it was the same as left by
> the BIOS.
> If I set everything uncacheable the system slows down by a factor of
> two - measured from top CPU usage seen in top.
> If I set it back to write-back it returns to previous usage, but it is
> still much slower than with 2G installed.
> Maybe MTRR is a red hering...
> But why are the Linux guys claim to fix this with MTRR settings?
> B.Walter <bernd at bwct.de> http://www.bwct.de
> Modbus/TCP Ethernet I/O Baugruppen, ARM basierte FreeBSD Rechner uvm.
B.Walter <bernd at bwct.de> http://www.bwct.de
Modbus/TCP Ethernet I/O Baugruppen, ARM basierte FreeBSD Rechner uvm.
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