issues with hwpmc and athlon XP

Joseph Koshy jkoshy at
Sun Mar 16 21:13:03 PDT 2008

> It seems that at least my revision of the Athlon XP has 48 bit
> performance counters (AMD Athlon Processor x86 Code Optimisation
> Guide, page 235 (Performance-Monitoring Counters: Overview) and the
> top 16 bits read back 0x0000.

Good catch.

> Since the code is taking the 2's compliment of the stored PMC value
> (which is so the value is incremented to 0xffffffffffffffff and wraps
> over, generating an NMI - mentioned on page 240), negating the value
> gives humerous results:

Thank you for the bug report and for the analysis in kern/121660.

It so happens that the Athlon XP machine I purchased had one of those
BIOSes that do not enable the local APIC.  So I couldn't get those
PMCs to deliver an interrupt and wasn't able to test sampling on this
processor.  That was frustrating, especially since Linux 2.4 and later
can override the BIOS and use the LAPIC; we can't.

Onto debugging this bug: my first question is: does system sampling
(i.e.. pmcstat -S) work OK on this CPU?

> (Oh and whilst I'm at it; maybe some documentation relating to your
> pmc debugging features would be nice. :)

Uhhh.  Well, its just scaffolding around printf(9) and is fairly
commented in hwpmc_mod.c.  You've already figured out most of the
stuff anyhow :).  Ask me in private mail if you want any more detail.
I don't know where else to document it; surely its not something worth
adding to the hwpmc.4 manual page :).


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