Marvell Yukon 2 88E8040

Pyun YongHyeon pyunyh at gmail.com
Mon Jun 16 07:18:27 UTC 2008


On Thu, Jun 12, 2008 at 08:02:42PM -0500, Stephen Montgomery-Smith wrote:
 > Pyun YongHyeon wrote:
 > >On Thu, Jun 12, 2008 at 03:07:56PM -0500, Stephen Montgomery-Smith wrote:
 > > > Bjoern A. Zeeb wrote:
 > > > >On Thu, 12 Jun 2008, Stephen Montgomery-Smith wrote:
 > > > >
 > > > >>I saw a Marvell Yukon 2 88E8040 driver at
 > > > >>http://people.freebsd.org/~yongari/msk/msk.88E8040.patch
 > >
 > >I guess patch above wouldn't apply cleanly due to changes in
 > >msk(4).
 > >
 > > > >>but the patch doesn't apply cleanly.
 > > > >>
 > > > >>Are people considering putting it into FreeBSD 8x or FreeBSD 7x 
 > > anytime
 > > > >>soon?
 > > > >
 > >
 > >Yes, I'd like to but had no testers so far. (I'm still waiting for
 > >feedback from a first tester.)
 > >Because I don't have 88E8040 hardware I need help from users to
 > >write a working patch. What make me hard for this hardware was it
 > >used slightly different descriptor format and added additional new
 > >silicon bugs.
 > >
 > >I'll update the patch in a couple of days and let you know.
 > 
 > Thanks.  And I'll test it for you.
 > 
 > I'm using FreeBSD CURRENT.

Ok, I've created patch for 88E8040 Yukon FE+. This controller
seems to be quite differnet one from previous generation of Yukon
II family. This controller uses completely different checksum
offload descriptor format(both Tx and Rx) as well as new TSO
scheme. While this one seems to use more simple approach than
that of old-style it deteriorates the complexity of configuration
of checksum offload and TSO.
As a result I'm not sure whether Tx checksum offload and TSO would
work with attached patch. It's too complex so I might miss some
important setup. If you encounter strange things with this patch
please turn off Tx checksum offload and TSO.
(e.g. #ifconfig msk0 -tso -txcsum)

-- 
Regards,
Pyun YongHyeon
-------------- next part --------------
--- sys/dev/msk/if_msk.c.orig	2008-03-27 13:43:51.000000000 +0900
+++ sys/dev/msk/if_msk.c	2008-06-16 15:55:39.000000000 +0900
@@ -195,6 +195,8 @@
 	    "Marvell Yukon 88E8038 Gigabit Ethernet" },
 	{ VENDORID_MARVELL, DEVICEID_MRVL_8039,
 	    "Marvell Yukon 88E8039 Gigabit Ethernet" },
+	{ VENDORID_MARVELL, DEVICEID_MRVL_8040,
+	    "Marvell Yukon 88E8040 Fast Ethernet" },
 	{ VENDORID_MARVELL, DEVICEID_MRVL_4361,
 	    "Marvell Yukon 88E8050 Gigabit Ethernet" },
 	{ VENDORID_MARVELL, DEVICEID_MRVL_4360,
@@ -219,6 +221,7 @@
         "Yukon Unknown",
         "Yukon EC",
         "Yukon FE"
+        "Yukon FE+"
 };
 
 static int mskc_probe(device_t);
@@ -927,12 +930,32 @@
 			error = EINVAL;
 			break;
 		}
-		if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE &&
-		    ifr->ifr_mtu > MSK_MAX_FRAMELEN) {
-			error = EINVAL;
-			break;
-		}
 		MSK_IF_LOCK(sc_if);
+		if (ifr->ifr_mtu > MSK_MAX_FRAMELEN) {
+			switch (sc_if->msk_softc->msk_hw_id) {
+			case CHIP_ID_YUKON_FE:
+			case CHIP_ID_YUKON_FE_P:
+				error = EINVAL;
+				break;
+			case CHIP_ID_YUKON_EC_U:
+				/*
+				 * In Yukon EC Ultra, TSO & checksum offload
+				 * is not supported for jumbo frame.
+				 */
+				ifp->if_hwassist &=
+				    ~(MSK_CSUM_FEATURES | CSUM_TSO);
+				ifp->if_capenable &=
+				    ~(IFCAP_TSO4 | IFCAP_TXCSUM);
+				VLAN_CAPABILITIES(ifp);
+				break;
+			default:
+				break;	
+			}
+		}
+		if (error != 0) {
+			MSK_IF_UNLOCK(sc_if);
+ 			break;
+ 		}
 		ifp->if_mtu = ifr->ifr_mtu;
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
 			msk_init_locked(sc_if);
@@ -973,23 +996,24 @@
 	case SIOCSIFCAP:
 		MSK_IF_LOCK(sc_if);
 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
-		if ((mask & IFCAP_TXCSUM) != 0) {
+		if ((mask & IFCAP_TXCSUM) != 0 &&
+		    (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
 			ifp->if_capenable ^= IFCAP_TXCSUM;
-			if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 &&
-			    (IFCAP_TXCSUM & ifp->if_capabilities) != 0)
+			if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
 				ifp->if_hwassist |= MSK_CSUM_FEATURES;
 			else
 				ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
 		}
-		if ((mask & IFCAP_VLAN_HWTAGGING) != 0) {
+		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
+		    (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 			msk_setvlan(sc_if, ifp);
 		}
 
-		if ((mask & IFCAP_TSO4) != 0) {
+		if ((mask & IFCAP_TSO4) != 0 &&
+		    (IFCAP_TSO4 & ifp->if_capabilities) != 0) {
 			ifp->if_capenable ^= IFCAP_TSO4;
-			if ((IFCAP_TSO4 & ifp->if_capenable) != 0 &&
-			    (IFCAP_TSO4 & ifp->if_capabilities) != 0)
+			if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
 				ifp->if_hwassist |= CSUM_TSO;
 			else
 				ifp->if_hwassist &= ~CSUM_TSO;
@@ -1041,14 +1065,14 @@
 {
 	int next;
 	int i;
-	uint8_t val;
 
 	/* Get adapter SRAM size. */
-	val = CSR_READ_1(sc, B2_E_0);
-	sc->msk_ramsize = (val == 0) ? 128 : val * 4;
+	sc->msk_ramsize = CSR_READ_1(sc, B2_E_0);
 	if (bootverbose)
 		device_printf(sc->msk_dev,
 		    "RAM buffer size : %dKB\n", sc->msk_ramsize);
+	if (sc->msk_ramsize == 0)
+		return (0);
 	/*
 	 * Give receiver 2/3 of memory and round down to the multiple
 	 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple
@@ -1081,7 +1105,7 @@
 static void
 msk_phy_power(struct msk_softc *sc, int mode)
 {
-	uint32_t val;
+	uint32_t our, val;
 	int i;
 
 	switch (mode) {
@@ -1107,16 +1131,18 @@
 
 		val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
 		val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
-		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
-		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
-			/* Deassert Low Power for 1st PHY. */
-			val |= PCI_Y2_PHY1_COMA;
-			if (sc->msk_num_port > 1)
-				val |= PCI_Y2_PHY2_COMA;
-		} else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
-			uint32_t our;
-
-			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
+		switch (sc->msk_hw_id) {
+		case CHIP_ID_YUKON_XL:
+			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
+				/* Deassert Low Power for 1st PHY. */
+				val |= PCI_Y2_PHY1_COMA;
+				if (sc->msk_num_port > 1)
+					val |= PCI_Y2_PHY2_COMA;
+			}
+			break;
+		case CHIP_ID_YUKON_EC_U:
+		case CHIP_ID_YUKON_FE_P:
+			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF);
 
 			/* Enable all clocks. */
 			pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4);
@@ -1127,6 +1153,9 @@
 			pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4);
 			/* Set to default value. */
 			pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4);
+			break;
+		default:
+			break;
 		}
 		/* Release PHY from PowerDown/COMA mode. */
 		pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
@@ -1486,14 +1515,24 @@
 	ether_ifattach(ifp, eaddr);
 	MSK_IF_LOCK(sc_if);
 
-	/*
-	 * VLAN capability setup 
-	 * Due to Tx checksum offload hardware bugs, msk(4) manually
-	 * computes checksum for short frames. For VLAN tagged frames
-	 * this workaround does not work so disable checksum offload
-	 * for VLAN interface.
-	 */
-	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
+	/* VLAN capability setup */
+	if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
+	    sc_if->msk_softc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
+		/*
+		 * Due to the FE+'s status writeback bug, msk(4) ignores
+		 * status word in msk_rxeof(). So msk(4) can't take
+		 * advantage of VLAN hardware assistance.
+		 */
+		ifp->if_capabilities |= IFCAP_VLAN_MTU;
+	} else {
+		/*
+		 * Due to Tx checksum offload hardware bugs, msk(4) manually
+		 * computes checksum for short frames. For VLAN tagged frames
+		 * this workaround does not work so disable checksum offload
+		 * for VLAN interface.
+		 */
+        	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
+	}
 	ifp->if_capenable = ifp->if_capabilities;
 
 	/*
@@ -1577,7 +1616,7 @@
 	sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
 	/* Bail out if chip is not recognized. */
 	if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
-	    sc->msk_hw_id > CHIP_ID_YUKON_FE) {
+	    sc->msk_hw_id > CHIP_ID_YUKON_FE_P) {
 		device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
 		    sc->msk_hw_id, sc->msk_hw_rev);
 		mtx_destroy(&sc->msk_mtx);
@@ -1634,6 +1673,9 @@
 	case CHIP_ID_YUKON_FE:
 		sc->msk_clock = 100;	/* 100 Mhz */
 		break;
+	case CHIP_ID_YUKON_FE_P:
+		sc->msk_clock = 50;	/* 50 Mhz */
+		break;
 	case CHIP_ID_YUKON_XL:
 		sc->msk_clock = 156;	/* 156 Mhz */
 		break;
@@ -2521,7 +2563,8 @@
 
 	tcp_offset = offset = 0;
 	m = *m_head;
-	if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) {
+	if ((sc_if->msk_softc->msk_hw_id != CHIP_ID_YUKON_FE_P) &&
+	    (m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) {
 		/*
 		 * Since mbuf has no protocol specific structure information
 		 * in it we have to inspect protocol information here to
@@ -2637,11 +2680,19 @@
 
 	/* Check TSO support. */
 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
-		tso_mtu = offset + m->m_pkthdr.tso_segsz;
+		/* FE+ uses different Op code and format. */
+		if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P)
+			tso_mtu = m->m_pkthdr.tso_segsz;
+		else
+			tso_mtu = offset + m->m_pkthdr.tso_segsz;
 		if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
 			tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
 			tx_le->msk_addr = htole32(tso_mtu);
-			tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER);
+			if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P)
+				tx_le->msk_control = htole32(OP_MSS | HW_OWNER);
+			else
+				tx_le->msk_control =
+				    htole32(OP_LRGLEN | HW_OWNER);
 			sc_if->msk_cdata.msk_tx_cnt++;
 			MSK_INC(prod, MSK_TX_RING_CNT);
 			sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
@@ -2665,15 +2716,22 @@
 	}
 	/* Check if we have to handle checksum offload. */
 	if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
-		tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
-		tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data)
-		    & 0xffff) | ((uint32_t)tcp_offset << 16));
-		tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER));
-		control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
-		if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
-			control |= UDPTCP;
-		sc_if->msk_cdata.msk_tx_cnt++;
-		MSK_INC(prod, MSK_TX_RING_CNT);
+		/* FE+ uses different checksum offload format. */
+		if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P) {
+			control |= CALSUM;
+		} else {
+			tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
+			tx_le->msk_addr = htole32(((tcp_offset +
+			    m->m_pkthdr.csum_data) & 0xffff) |
+			    ((uint32_t)tcp_offset << 16));
+			tx_le->msk_control = htole32(1 << 16 |
+			    (OP_TCPLISW | HW_OWNER));
+			control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
+			if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
+				control |= UDPTCP;
+			sc_if->msk_cdata.msk_tx_cnt++;
+			MSK_INC(prod, MSK_TX_RING_CNT);
+		}
 	}
 
 	si = prod;
@@ -2939,11 +2997,28 @@
 		if (len > sc_if->msk_framesize ||
 		    ((status & GMR_FS_ANY_ERR) != 0) ||
 		    ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
-			/* Don't count flow-control packet as errors. */
-			if ((status & GMR_FS_GOOD_FC) == 0)
-				ifp->if_ierrors++;
-			msk_discard_rxbuf(sc_if, cons);
-			break;
+			if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
+			    sc_if->msk_softc->msk_hw_rev ==
+			    CHIP_REV_YU_FE_P_A0) {
+				/*
+				 * XXX
+				 * According to Linux, this FE+ generates
+				 * bogus status LEs so it cannot rely on
+				 * hardware status. Let upper layer handle
+				 * recevied frame with minimal check.
+				 */
+				if (rxlen > MSK_MAX_FRAMELEN) {
+					ifp->if_ierrors++;
+					msk_discard_rxbuf(sc_if, cons);
+				}
+			} else {
+				/* Don't count flow-control packet as errors. */
+				if ((status & GMR_FS_GOOD_FC) == 0)
+					ifp->if_ierrors++;
+				msk_discard_rxbuf(sc_if, cons);
+				break;
+			}
+
 		}
 		rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
 		m = rxd->rx_m;
@@ -3561,6 +3636,7 @@
 	struct mii_data	 *mii;
 	uint16_t eaddr[ETHER_ADDR_LEN / 2];
 	uint16_t gmac;
+	uint32_t reg;
 	int error, i;
 
 	MSK_IF_LOCK_ASSERT(sc_if);
@@ -3649,8 +3725,11 @@
 	/* Configure Rx MAC FIFO. */
 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
-	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
-	    GMF_OPER_ON | GMF_RX_F_FL_ON);
+	reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
+	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
+	    sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
+		reg |= GMF_RX_OVER_ON;
+	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
 
 	/* Set promiscuous mode. */
 	msk_setpromisc(sc_if);
@@ -3666,8 +3745,12 @@
 	 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
 	 * due to hardware hang on receipt of pause frames.
 	 */
-	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR),
-	    RX_GMF_FL_THR_DEF + 1);
+	reg = RX_GMF_FL_THR_DEF + 1;
+	/* Another magic for Yukon FE+. - From Linux. */
+	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
+	    sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
+		reg = 0x178;
+	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
 
 	/* Configure Tx MAC FIFO. */
 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
@@ -3677,21 +3760,28 @@
 	/* Configure hardware VLAN tag insertion/stripping. */
 	msk_setvlan(sc_if, ifp);
 
-	if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
+	if (sc->msk_ramsize == 0) {
 		/* Set Rx Pause threshould. */
 		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
 		    MSK_ECU_LLPP);
 		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
 		    MSK_ECU_ULPP);
 		if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) {
-			/*
-			 * Set Tx GMAC FIFO Almost Empty Threshold.
-			 */
-			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
-			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
-			/* Disable Store & Forward mode for Tx. */
-			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
-			    TX_JUMBO_ENA | TX_STFW_DIS);
+			if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) {
+				/*
+				 * Set Tx GMAC FIFO Almost Empty Threshold.
+				 */
+				CSR_WRITE_4(sc,
+				    MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
+				    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
+				/* Disable Store & Forward mode for Tx. */
+				CSR_WRITE_4(sc,
+				    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
+				    TX_JUMBO_ENA | TX_STFW_DIS);
+			} else
+				CSR_WRITE_4(sc,
+				    MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
+				    TX_JUMBO_ENA | TX_STFW_ENA);
 		} else {
 			/* Enable Store & Forward mode for Tx. */
 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
@@ -3699,6 +3789,14 @@
 		}
 	}
 
+	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
+	    sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
+		/* Disable dynamic watermark - from Linux. */
+		reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
+		reg &= ~0x03;
+		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
+	}
+
 	/*
 	 * Disable Force Sync bit and Alloc bit in Tx RAM interface
 	 * arbiter as we don't use Sync Tx queue.
@@ -3790,6 +3888,8 @@
 	int ltpp, utpp;
 
 	sc = sc_if->msk_softc;
+	if (sc->msk_ramsize == 0)
+		return;
 
 	/* Setup Rx Queue. */
 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
--- sys/dev/msk/if_mskreg.h.orig	2008-02-29 12:38:12.000000000 +0900
+++ sys/dev/msk/if_mskreg.h	2008-06-16 13:01:28.000000000 +0900
@@ -130,7 +130,8 @@
 #define DEVICEID_MRVL_8035	0x4350
 #define DEVICEID_MRVL_8036	0x4351
 #define DEVICEID_MRVL_8038	0x4352
-#define DEVICEID_MRVL_8039	0X4353
+#define DEVICEID_MRVL_8039	0x4353
+#define DEVICEID_MRVL_8040	0x4354
 #define DEVICEID_MRVL_4360	0x4360
 #define DEVICEID_MRVL_4361	0x4361
 #define DEVICEID_MRVL_4362	0x4362
@@ -828,6 +829,7 @@
 #define CHIP_ID_YUKON_EC_U	0xb4 /* Chip ID for YUKON-2 EC Ultra */
 #define CHIP_ID_YUKON_EC	0xb6 /* Chip ID for YUKON-2 EC */
 #define CHIP_ID_YUKON_FE	0xb7 /* Chip ID for YUKON-2 FE */
+#define CHIP_ID_YUKON_FE_P	0xb8 /* Chip ID for YUKON-2 FE+ */
 
 #define	CHIP_REV_YU_XL_A0	0 /* Chip Rev. for Yukon-2 A0 */
 #define	CHIP_REV_YU_XL_A1	1 /* Chip Rev. for Yukon-2 A1 */
@@ -841,6 +843,8 @@
 #define	CHIP_REV_YU_EC_U_A0	1
 #define	CHIP_REV_YU_EC_U_A1	2
 
+#define	CHIP_REV_YU_FE_P_A0	0 /* Chip Rev. for Yukon-2 FE+ A0 */
+
 /*	B2_Y2_CLK_GATE	 8 bit	Clock Gating (Yukon-2 only) */
 #define Y2_STATUS_LNK2_INAC	BIT_7	/* Status Link 2 inactiv (0 = activ) */
 #define Y2_CLK_GAT_LNK2_DIS	BIT_6	/* Disable clock gating Link 2 */
@@ -1847,6 +1851,10 @@
 #define RX_TRUNC_OFF		BIT_26	/* disable packet truncation */
 #define RX_VLAN_STRIP_ON	BIT_25	/* enable  VLAN stripping */
 #define RX_VLAN_STRIP_OFF	BIT_24	/* disable VLAN stripping */
+#define	GMF_RX_OVER_ON		BIT_19	/* enable flushing on receive overrun */
+#define	GMF_RX_OVER_OFF		BIT_18	/* disable flushing on receive overrun */
+#define	GMF_ASF_RX_OVER_ON	BIT_17	/* enable flushing of ASF when overrun */
+#define	GMF_ASF_RX_OVER_OFF	BIT_16	/* disable flushing of ASF when overrun */
 #define GMF_WP_TST_ON		BIT_14	/* Write Pointer Test On */
 #define GMF_WP_TST_OFF		BIT_13	/* Write Pointer Test Off */
 #define GMF_WP_STEP		BIT_12	/* Write Pointer Step/Increment */
@@ -2114,6 +2122,8 @@
 #define OP_ADDR64VLAN	(OP_ADDR64 | OP_VLAN)
 #define OP_LRGLEN	0x24000000
 #define OP_LRGLENVLAN	(OP_LRGLEN | OP_VLAN)
+#define OP_MSS		0x28000000
+#define OP_MSSVLAN	(OP_MSS | OP_VLAN)
 #define OP_BUFFER	0x40000000
 #define OP_PACKET	0x41000000
 #define OP_LARGESEND	0x43000000


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