Topology aware scheduling algorithm.

Jeff Roberson jroberson at
Tue Feb 26 02:21:46 UTC 2008

Also in the cpuset.diff at:

There is support for cpu topology aware scheduling.  This allows the 
scheduler to know which cores are colocated on packages and what the cache 
arrangement between them is.

We have seen big improvements in some workloads and some reduction in 
other workloads.  However, I believe this should finally close the gap on 
the few benchmarks where ULE could trail 4BSD.  Please prove me wrong if 
you can so I can continue to make ULE better.

Right now the MD code is slightly lagging behind what the scheduler can 
utilize.  If you have an interest in digging through processor 
documentation to write code to detect more information about the caches 
please contact me.  I'd love some help.

This code and the cpusets will likely be committed to 8.0 by the end of 
the week and then we'll discuss MFCs after some time to settle there.


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