svn commit: r185756 - head/sys/dev/re

[Anton Yuzhaninov]

Pyun YongHyeon wrote:
> Author: yongari
> Date: Mon Dec  8 02:48:41 2008
> New Revision: 185756
> URL: http://svn.freebsd.org/changeset/base/185756
> 
> Log:
>   Reduce spin wait time consumed in GMII register access routines.
>   Waiting for 1ms for each GMII register access looks overkill and it
>   may also decrease overall performance of driver because re(4)
>   invokes mii_tick for every hz.
>   
>   Tested by:	rpaulo
> 
> Modified:
>   head/sys/dev/re/if_re.c
> 
> Modified: head/sys/dev/re/if_re.c
> ==============================================================================
> --- head/sys/dev/re/if_re.c	Mon Dec  8 02:38:13 2008	(r185755)
> +++ head/sys/dev/re/if_re.c	Mon Dec  8 02:48:41 2008	(r185756)
> @@ -417,13 +417,12 @@ re_gmii_readreg(device_t dev, int phy, i
>  	}
>  
>  	CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
> -	DELAY(1000);
>  
>  	for (i = 0; i < RL_TIMEOUT; i++) {
> +		DELAY(30);
>  		rval = CSR_READ_4(sc, RL_PHYAR);
>  		if (rval & RL_PHYAR_BUSY)
>  			break;
> -		DELAY(100);
>  	}
>  
>  	if (i == RL_TIMEOUT) {
> @@ -445,13 +444,12 @@ re_gmii_writereg(device_t dev, int phy, 
>  
>  	CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
>  	    (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
> -	DELAY(1000);
>  
>  	for (i = 0; i < RL_TIMEOUT; i++) {
> +		DELAY(30);
>  		rval = CSR_READ_4(sc, RL_PHYAR);
>  		if (!(rval & RL_PHYAR_BUSY))
>  			break;
> -		DELAY(100);
>  	}
>  
>  	if (i == RL_TIMEOUT) {

After this commit I see in logs errors:

Dec 10 21:37:42 citrin kernel: re0: PHY read failed
Dec 10 21:38:05 citrin last message repeated 3 times
Dec 10 21:38:44 citrin last message repeated 3 times
Dec 10 21:38:44 citrin kernel: re0: link state changed to DOWN
Dec 10 21:38:45 citrin kernel: re0: link state changed to UP
Dec 10 21:38:55 citrin kernel: re0: PHY read failed
Dec 10 21:39:38 citrin last message repeated 3 times
Dec 10 21:39:38 citrin kernel: re0: link state changed to DOWN
Dec 10 21:39:39 citrin kernel: re0: link state changed to UP
Dec 10 21:40:09 citrin kernel: re0: PHY read failed
Dec 10 21:40:21 citrin kernel: re0: PHY read failed
Dec 10 21:41:03 citrin kernel: re0: PHY read failed

I tried to revert this patch - errors disappeared.

HW:

re0 at pci0:2:5:0: class=0x020000 card=0xe0001458 chip=0x816710ec rev=0x10 hdr=0x00
     vendor     = 'Realtek Semiconductor'
     device     = 'RTL8169/8110 Family Gigabit Ethernet NIC'
     class      = network
     subclass   = ethernet
     cap 01[dc] = powerspec 2  supports D0 D1 D2 D3  current D0

from dmesg:
re0: <RealTek 8169SC/8110SC Single-chip Gigabit Ethernet> port 0xa000-0xa0ff mem 
0xe1000000-0xe10000ff irq 21 at device 5.0 on pci2
re0: Chip rev. 0x18000000
re0: MAC rev. 0x00000000

-- 
  Anton Yuzhaninov