The relation between %fs and fs base

Jung-uk Kim jkim at
Mon Jun 25 22:51:24 UTC 2007

On Monday 25 June 2007 01:37 pm, jj shen wrote:
> Hi,
> I want to access different TLS through both fs base and GDT
> simultaneously. Let us call the two ways TLS_FSBASE and TLS_GDT
> respectively.
> (1) Can I switch from TLS_FSBASE to TLS_GDT just by: "movl GDT_SEL,
> %fs" (where GDT_SEL is the selector of GDT entry)?
> Will this instruction destroy the content of the IA32_FS_BASE MSR?
> (2) When switching from TLS_GDT to TLS_FSBASE, can I just set %fs
> to zero to indicate the fs base should be used, or must I invoke
> the
> *wrmsrl*instruction to reset IA32_FS_BASE once again?
> (3) What is the length of %fs? What I get by "movl %fs, %eax" in
> %eax? In the programmer manual from AMD, it is said somewhere that
> segment registers are still 16 bits as in x86, and it is also said
> otherwhere that "segment loads into FS and GS load a standard
> 32-bit base value in the hidden portion of the segment descriptor
> register".
>  (4) What is the content of %fs, a descriptor selector or a base
> address smaller than 0xffffffff?
> What is effect of "movl val, %fs", loading a GDT selector or a
> 32-bit base address to %fs?
>     Seen from the citation above, I think *val *should be a 32-bit
> base address; however seen from the implementation of Linux
> *arch_prctl* system call, it is a GDT selector loaded into %fs.

I don't know what you are trying to achieve but don't mess up with %fs 
and %gs on amd64 unless you are absolutely sure.  It is deprecated 
and it won't work as you expected.  The only way to get/set %fs and 
%gs properly on amd64 is via proper API, i.e., sysarch(2) with 
AMD64_{GET,SET}_{FS,GS}BASE.  If you use the API, the MSR will be 
properly saved and restored while switching contexts.  However, it is 
very much discouraged as the manual page says, e. g., it will cause 
serious problem if the application is threaded, etc.  In fact, the 
API should be only used by threading libraries.

Jung-uk Kim

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