FreeBSD is now self-hosting on the UltraSPARC T1

[Chad Leigh -- Shire.Net LLC]

On May 22, 2006, at 10:34 AM, Eric Anderson wrote:

> Chad Leigh -- Shire.Net LLC wrote:
>> On May 21, 2006, at 7:54 PM, m m wrote:
>>> While
>>> on topic, the Opterons aren't SMP either, and neither are the
>>> ht-Xeons...
>> I would like t\o hear the rational for the Opterons (presumably  
>> the dual core ones) not being SMP.  They have two independent  
>> operating cores in one physical package.  Who cares how it is  
>> packaged?  I would tend to agree with you on the ht-Xeon in terms  
>> of general descriptions.  I do not know as well how the ht-xeon  
>> work as I don't use any but it seems to me that the "SMP" moniker,  
>> at least in FreeBSD, relate to how things are scheduled.
>> Btw, Opteron MB with a single dual-core ship get a BIOS report on  
>> Boot of having 2 CPUs...
>
> Careful - two cores doesn't mean two caches, and isn't always just  
> 'two cores glued into one package'.
>

But on the Opteron, the subject of the discussion, it does.  They  
have two caches. The Intel Core Duo dies not.

Chad

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Chad Leigh -- Shire.Net LLC
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