AMD cache values for page colouring

[Antoine Brodin]

Alexander Leidinger <Alexander at Leidinger.net> wrote:
> Divacky Roman <xdivac02 at stud.fit.vutbr.cz> wrote:
> [no cachesize detection]
> > my CPU is:
> > CPU: AMD Athlon(tm) XP 2500+ (1834.88-MHz 686-class CPU)
> > Origin = "AuthenticAMD"  Id = 0x6a0  Stepping = 0
> > Features=0x383fbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,MMX,FXSR,SSE>
> > AMD Features=0xc0400800<SYSCALL,MMX+,3DNow+,3DNow>
> 
> So the AMD64 code works (on AMD processors) but the IA32 (on AMD) fails.
> Either I did something completely wrong, or it's a small typo I do overlook
> (tomatoes on the eyes...). Can someone with a little bit of AMD feature
> detection knowledge have a look at:

Hi Alexander,

The detection doesn't work because the cpu_exthigh variable isn't
initialized.
And if you and *ways with 0x0f, it will never be 255.

Cheers,

Antoine

PS: with the attached path I've got
> sysctl vm.stats.pagequeue
vm.stats.pagequeue.page_colors: 16
vm.stats.pagequeue.cachesize: 512
vm.stats.pagequeue.cachenways: 8
vm.stats.pagequeue.prime1: 5
vm.stats.pagequeue.prime2: 3

Index: i386/i386/identcpu.c
===================================================================
RCS file: /home/ncvs/src/sys/i386/i386/identcpu.c,v
retrieving revision 1.152
diff -u -p -r1.152 identcpu.c
--- i386/i386/identcpu.c	31 Dec 2005 14:39:17 -0000	1.152
+++ i386/i386/identcpu.c	2 Jan 2006 20:09:48 -0000
@@ -1425,14 +1425,15 @@ print_INTEL_TLB(u_int data)
 
 static void
 setPQL2_AMD(int *const size, int *const ways) {
-	if (cpu_exthigh >= 0x80000006) {
-		u_int regs[4];
+	u_int regs[4];
 
+	do_cpuid(0x80000000, regs);
+	if (regs[0] >= 0x80000000)
+		cpu_exthigh = regs[0];
+	if (cpu_exthigh >= 0x80000006) {
 		do_cpuid(0x80000006, regs);
 		*size = regs[2] >> 16;
 		*ways = (regs[2] >> 12) & 0x0f;
-		if(*ways == 255)		/* fully associative */
-			*ways = 1;
 	}
 }