Higher interrupt rate after recent SMP/APIC timer changes?
Daniel Eriksson
daniel_k_eriksson at telia.com
Fri Mar 11 14:52:00 PST 2005
After the recent changes to the use of APIC timers on SMP systems, the
reported interrupt rate has gone up significantly:
# vmstat -i
interrupt total rate
irq1: atkbd0 3 0
irq0: clk 55294842 1998
irq4: sio0 656 0
irq6: fdc0 13 0
irq13: npx0 1 0
irq14: ata0 28299 1
irq15: ata1 28144 1
irq17: atapci1+ 60822 2
irq19: atapci3+ 19848 0
irq20: ciss0 857173 30
irq21: em0 1 0
irq22: em1 1 0
lapic1: timer 110665583 3998
lapic0: timer 110649350 3998
Total 277604736 10031
This is an SMP box (dual AMD AthlonMP) running with HZ=2000 and POLLING
enabled. Should I worry about the 4k intr/sec reported for lapic0 and
lapic1, or is this the way things should be?
I should add that system load has not changed noticeably, leading me to
believe that the lapic* interrupt rate is by design and nothing to worry
about. (But I still wanted to ask.)
/Daniel Eriksson
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