How to determine the L2 cache size on non-AMD CPUs (automatic
page queue color tuning)?
John Polstra
jdp at polstra.com
Wed Jun 16 16:11:47 GMT 2004
On 16-Jun-2004 Alexander Leidinger wrote:
> Hi,
>
> I'm working with Alan and Chad David on automatic tuning of the number
> of colors for the page queue. For AMD CPUs (including amd64, but not
> tested) we already have code in identcpu.c to determine the size of the
> L2 cache and its associativity.
>
> Now I need to know how to determine those properties on at least some
> Intel CPUs (e.g. P3 & P4).
>
> Since Intel has a lot of manuals and everyone contains a lot of pages, I
> decided to first ask here if someone can give me a pointer please (or
> working code).
Check out the "misc/cpuid" port. Here's some sample output from a
PIII system. Cache information is at the end.
eax in eax ebx ecx edx
00000000 00000002 756e6547 6c65746e 49656e69
00000001 000006b1 00000004 00000000 0383fbff
00000002 03020101 00000000 00000000 0c040883
80000000 80000004 00000000 00000000 00000000
80000001 00000000 00000000 00000000 00000000
80000002 65746e49 2952286c 6e655020 6d756974
80000003 20295228 20494949 20555043 696d6166
80000004 2020796c 20202020 33333131 007a484d
Vendor ID: "GenuineIntel"; CPUID level 2
Intel-specific functions:
Version 000006b1:
Type 0 - Original OEM
Family 6 - Pentium Pro
Model 11 -
Stepping 1
Reserved 0
Brand index: 4 [brand 4]
Extended brand string: "Intel(R) Pentium(R) III CPU family 1133MHz"
Feature flags 0383fbff:
FPU Floating Point Unit
VME Virtual 8086 Mode Enhancements
DE Debugging Extensions
PSE Page Size Extensions
TSC Time Stamp Counter
MSR Model Specific Registers
PAE Physical Address Extension
MCE Machine Check Exception
CX8 COMPXCHG8B Instruction
APIC On-chip Advanced Programmable Interrupt Controller present and enabled
SEP Fast System Call
MTRR Memory Type Range Registers
PGE PTE Global Flag
MCA Machine Check Architecture
CMOV Conditional Move and Compare Instructions
FGPAT Page Attribute Table
PSE-36 36-bit Page Size Extension
MMX MMX instruction set
FXSR Fast FP/MMX Streaming SIMD Extensions save/restore
SSE Streaming SIMD Extensions instruction set
TLB and cache info:
01: Instruction TLB: 4KB pages, 4-way set assoc, 32 entries
02: Instruction TLB: 4MB pages, 4-way set assoc, 2 entries
03: Data TLB: 4KB pages, 4-way set assoc, 64 entries
83: 2nd-level cache: 512KB, 8-way set assoc 32 byte line size
08: 1st-level instruction cache: 16KB, 4-way set assoc, 32 byte line size
04: Data TLB: 4MB pages, 4-way set assoc, 8 entries
0c: 1st-level data cache: 16KB, 4-way set assoc, 32 byte line size
John
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